Error-[ICPD_INIT] Illegal combination of drivers ../../common/caravel_project/rtl/verilog/mgmt_core.patrick.v, 103 Illegal combination of procedural drivers Variable "mgmtsoc_interrupt" is driven by an invalid combination of procedural drivers. Variables written on left-hand of "always_comb" cannot be written to by any other processes, including other "always_comb" processes. This variable is declared at "../../common/caravel_project/rtl/verilog/mgmt_core.patrick.v", 103: reg [31:0] mgmtsoc_interrupt;

20240207 update final solution - update verilog code - create a MUX instance from MUX in EDK lib and set dont_touch then synthesis tool keep this MUX instance for source_object of create_generated_clock Summmary issue 1: MUX output pin name(cell name) is changed after compile When the source_objects of create_generated_clock is a MUX output pinThe MUX output pin name is changed after compile. I suspect the MUX cell is GETCH type and after compile, the MUX cell is mapping to target library. It means the MUX output pin always changed after compile.how to provide MUX output pin name in sdc file?[workaround] create_generated_clock & compile 2nd times for patch MUX output pin name(cell name) changed issue issue 2: timing false path issue fixed by set_false_path

issue caravel provide some sdc file for signoff I need to update it for create sdc file for synthesis. Question: sdc files for signoff in caravel? 6817 should be created after synthsis set_case_analysis 0 [get_pins {chip_core/housekeeping/_6817_/Q}] code link set_case_analysis

caravel io spec log files for sdc log files sdc file study sdc file study update sdc for wbbd_sck create_clock -name clk -period $clk_period [get_ports {clock}]

check_timing warning Information: Checking unconstrained_endpoints... Warning: The following end-points are not constrained for maximum delay. End point --------------- mprj/u_fsic/U_AXIL_AXIS0/axi_ctrl_logic/data_ss_reg[0]/D gl

referenceOpenLane Overview - Youtube configuration.md openlane document step 1. get the docker command from run_fsic.log search by vimgrep 'docker run -it -v' % in viit should be match 2 items as belowuser_proj_example user_project_wrapper docker run -it -v $(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..):$(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..) -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/openlane_src:/openlane -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -e PDK_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -e PDK=sky130A -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -e OPENLANE_RUN_TAG=23_10_05_17_27 -e MCW_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -u 1000:1000 \ efabless/openlane:2022.11.19 sh -c "flow.tcl -design $(realpath ./user_proj_example) -save_path $(realpath ..) -save -tag 23_10_05_17_27 -overwrite -ignore_mismatches"

git clone https://github.com/TonyHo722/bash_study git clone http://TonyHo@61.66.242.171/r/linux-xlnx git clone http://github.com/Xilinx/linux-xlnx command git clone https://github.com/TonyHo722/bash_study cd bash_study git remote rename origin upstream

image GPIO_MPRJ_IO.by.Willy.pdf in joplin reference [2023-03-29] Study Topic - GPIO MPRJ IO by Willy Start from Makefile in caravel_user_project ifeq ($(PDK),sky130A)

AA code cause make user_proj_example fail issue in [STEP 1] - Running Synthesisfixed by update AA code AS code cause make user_proj_example fail issue in [STEP 14] - Running Detailed Placement hurry is debugging it irq port cause make user_proj_example fail issue in [STEP 36] - Running OpenROAD Antenna Rule Checker root casue is confirmed

main repo in tag=mpw-8c https://github.com/efabless/caravel_user_project/tree/mpw-8c sub-module in tag=mpw-8c https://github.com/efabless/caravel-lite/tree/mpw-8c https://github.com/efabless/caravel_mgmt_soc_litex/tree/mpw-8c caravel.v https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v caravan.v

trace code for caravel_user_project mpw-8c this document in below is code trace in https://github.com/efabless/caravel and may not sync to mpw-8c. Caravel reset pin [Tony] resetb come from testbench when no defined TOP_ROUTING and connect to sky130_fd_io__top_xres4v2 resetb_pad. the resetb_pad output resetb_core_h to caravel.v I suspect in silicon, it should defined TOP_ROUTING, the reset pin is connect to resetb_pad trace resetb signal

run_la_test1 - Integrate a gcd exmaple RTL design to Caravel SoC run_fsic - Integrate a fsic RTL design to Caravel SoC please reference bol-edu/caravel-lab for more tail information in caravel-lab 1. Download docket image(efabless/mpw_precheck) this image is not found in docker server when build caravel_user_project. reference this link for the detail Download docket image by web browser down mpw_precheck_mpw8c.tgz (the docker image is comefrom the machine run the carave_user_project building flow on Jan 2023)

dsn/rtl/fsic.v USER_SUBSYS #(.pADDR_WIDTH( pADDR_WIDTH ), .pDATA_WIDTH( 32 )) U_USER_SUBSYS0 ( ... ); User project in user_subsys.all.v dsn/rtl/user_subsys.all.v module USER_SUBSYS #( parameter pADDR_WIDTH = 12,

fail log commit found this issue after after add AA code fail log run_fsic.log hold violation hold violation fail log in run_fsic.log port ``irq'' is not a port of mprj irq issue fail log in run_fsic.log

FSIC ASIC Integration & Implementation Status - 20230918 after hack some design in AA, AS and testbench then fsic run openlane flow pass.pass logrun_fsic.log Successfully remade target file 'run-precheck'. build fsic in caravel-lab issue when no user_proj_example pass user_project_wrapper -> user_proj_example -> fsic fail

gcd example in caravel-lab user_project_wrapper -> user_proj_example -> seq_gcd pass case in fsic user_project_wrapper -> user_proj_example -> fsic error case in fsic user_project_wrapper -> fsic maybe need update some config file to support "no user_proj_example"

Error log 1. event triggerd issue system_test111_tb.v:850: error: Event name soc_to_fpga_axilite_read_cpl_event can't have member names (triggered) system_test111_tb.v:850: internal error: incomprehensible wait expression width (0). system_test111_tb.v:983: error: Event name soc_to_fpga_mailbox_write_event can't have member names (triggered) system_test111_tb.v:983: internal error: incomprehensible wait expression width (0). 2. assignment issue axi_ctrl_logic.sv:311: error: This assignment requires an explicit cast. reference this commit for patch.

the build process in bol-edu/caravel-lab was verify on Mar 13 2023 in this commit. When I want to try in on Sep 2023, something is differnt and CAN NOT build successfully base on the README.md in bol-edu/caravel-lab. please reference the caravel-lab setup update for how to workaound it. please reference the run "make caravel-sta" error - When using git clone -b mpw-8c https://github.com/efabless/caravel_user_project for this issue. Using auto build script execution build process for la_test1 git clone

When get project from git clone -b mpw-8c https://github.com/efabless/caravel_user_project error log when run "make caravel-sta" exec> read_spef -path chip_core/soc.core.RAM128 /home/tonyho/workspace/debug/d3_caravel_user_project/caravel_user_project/mgmt_core_wrapper/signoff/RAM128/openlane-signoff/spef/RAM128.nom.spef Error: timing_top.tcl line 60, path instance 'chip_core/soc.core.RAM128' not found. make[1]: *** [/home/tonyho/workspace/debug/d3_caravel_user_project/caravel_user_project/deps/timing-scripts/timing.mk:244: caravel-timing-typ-nom] Error 1 workaround in https://github.com/TonyHo722/timing-scripts (base) tonyho@ubuntu5:~/workspace/debug/d3_caravel_user_project/caravel_user_project/deps/timing-scripts$ git log 3538543 -p commit 3538543df11047ed7b8ad329d931fa138dcc3ff1 (main) Author: tonyho <TonyHo@via.com.tw>

issue commit link cause fail fixed commit link compare 3 version of rtl.f