# TOP in fsic.v
[dsn/rtl/fsic.v](https://github.com/TonyHo722/fsic_tony/blob/main/dsn/rtl/fsic.v#L461C1-L462C51)

USER_SUBSYS #(.pADDR_WIDTH( pADDR_WIDTH ),
              .pDATA_WIDTH( 32 )) U_USER_SUBSYS0 (
...
);

# User project in user_subsys.all.v
[dsn/rtl/user_subsys.all.v](https://github.com/TonyHo722/fsic_tony/blob/main/dsn/rtl/user_subsys.all.v#L343C1-L346C2)

module USER_SUBSYS #( parameter pADDR_WIDTH   = 12,
                      parameter pDATA_WIDTH   = 32
                    )
(
...
);


USER_PRJ #(.pADDR_WIDTH( 12 ),
           .pDATA_WIDTH( 32 )) U_USRPRJ0 (
...			
);

## update USER_PRJ module

module USER_PRJ #( parameter pADDR_WIDTH   = 12,
                   parameter pDATA_WIDTH   = 32
                 )
(
...
);

## TODO - remove test code

wire axi_awvalid_in;
wire axi_wvalid_in;

reg [31:0] RegisterData;

//write addr channel
assign 	axi_awvalid_in	= axi_awvalid && cc_up_enable;
wire axi_awready_out;
assign axi_awready = axi_awready_out;

//write data channel
assign 	axi_wvalid_in	= axi_wvalid && cc_up_enable;
wire axi_wready_out;
assign axi_wready = axi_wready_out;

// if both axi_awvalid_in=1 and axi_wvalid_in=1 then output axi_awready_out = 1 and axi_wready_out = 1
assign axi_awready_out = (axi_awvalid_in && axi_wvalid_in) ? 1 : 0;
assign axi_wready_out = (axi_awvalid_in && axi_wvalid_in) ? 1 : 0;

assign axi_arready = 1;

assign axi_rvalid = 1;
assign axi_rdata =  RegisterData;

//write register
always @(posedge axi_clk or negedge axi_reset_n)  begin
  if ( !axi_reset_n ) begin
    RegisterData <= 32'haa55aa55;
  end
  else begin
    if ( axi_awvalid_in && axi_wvalid_in ) begin		//when axi_awvalid_in=1 and axi_wvalid_in=1 means axi_awready_out=1 and axi_wready_out=1
      if (axi_awaddr[11:2] == 10'h000 ) begin //offset 0
        if ( axi_wstrb[0] == 1) RegisterData[7:0] <= axi_wdata[7:0];
        if ( axi_wstrb[1] == 1) RegisterData[15:8] <= axi_wdata[15:8];
        if ( axi_wstrb[2] == 1) RegisterData[23:16] <= axi_wdata[23:16];
        if ( axi_wstrb[3] == 1) RegisterData[31:24] <= axi_wdata[31:24];  
      end
      else begin
        RegisterData <= RegisterData;
      end
    end
  end
end

[code link](https://github.com/TonyHo722/fsic_tony/blob/main/dsn/rtl/user_subsys.all.v#L275)

# test bench
[dsn/testbench/tb_fsic.v](https://github.com/TonyHo722/fsic_tony/blob/main/dsn/testbench/tb_fsic.v#L338C3-L338C37)
test002 -> test002_fpga_axis_req

test002();	//test002_fpga_axis_req

- test002

	task test002;		//test002_fpga_axis_req
		//input [7:0] compare_data;

		begin
			for (i=0;i<CoreClkPhaseLoop;i=i+1) begin
				$display("test002: fpga_axis_req - loop %02d", i);
				fork 
					soc_apply_reset(40+i*10, 40);			//change coreclk phase in soc
					fpga_apply_reset(40,40);		//fix coreclk phase in fpga
				join
				#40;

				fpga_as_to_is_init();
				
				//soc_cc_is_enable=1;
				fpga_cc_is_enable=1;
				fork 
					soc_is_cfg_write(0, 4'b0001, 1);				//ioserdes rxen
					fpga_cfg_write(0,1,1,0);
				join
				$display($time, "=> soc rxen_ctl=1");
				$display($time, "=> fpga rxen_ctl=1");

				#400;
				fork 
					soc_is_cfg_write(0, 4'b0001, 3);				//ioserdes txen
					fpga_cfg_write(0,3,1,0);
				join
				$display($time, "=> soc txen_ctl=1");
				$display($time, "=> fpga txen_ctl=1");

				#200;
				fpga_as_is_tdata = 32'h5a5a5a5a;
				#40;
				#200;

				test002_fpga_axis_req();		//target to Axis Switch

				#200;
			end
		end
	endtask

[code link](https://github.com/TonyHo722/fsic_tony/blob/main/dsn/testbench/tb_fsic.v#L1154C1-L1195C99)

- test002_fpga_axis_req

	task test002_fpga_axis_req;
		//input [7:0] compare_data;

		//FPGA to SOC Axilite test
		begin
			//force User project up_as_tready = 1;
			force dut.AXIS_SW0.up_as_tready = 1;

			@ (posedge fpga_coreclk);
			fpga_as_is_tready <= 1;
			
			for(idx3=0; idx3<32; idx3=idx3+1)begin		//
				fpga_axis_req(32'h11111111 * (idx3 & 32'h0000_000F), TID_DN_UP);		//target to User Project
				//if (idx3 > 12 ) 			force dut.AXIS_SW0.up_as_tready = 1;
			end
			release dut.AXIS_SW0.up_as_tready;
			
			$display($time, "=> test002_fpga_axis_req done");
		end
	endtask

[code link](https://github.com/TonyHo722/fsic_tony/blob/main/dsn/testbench/tb_fsic.v#L1199C1-L1218C9)

## soc_axis_loopback - remove it

initial begin
	//connect_fpga_soc_serdes();
	soc_axis_loopback();
end

	task soc_axis_loopback;
		//input [31:0] data;
		//input [1:0] tid;
		begin
			$display($time, "=> soc_axis_loopback force dut.AXIS_SW0.up_as_tvalid = 1");
			force dut.AXIS_SW0.up_as_tvalid = dut.AXIS_SW0.as_up_tvalid;
			force dut.AXIS_SW0.up_as_tdata = dut.AXIS_SW0.as_up_tdata;
			force dut.AXIS_SW0.up_as_tstrb =  dut.AXIS_SW0.as_up_tstrb;
			force dut.AXIS_SW0.up_as_tkeep =  dut.AXIS_SW0.as_up_tkeep;
			//force dut.AXIS_SW0.up_as_tid =    dut.AXIS_SW0.as_up_tid;
			force dut.AXIS_SW0.up_as_tuser =  dut.AXIS_SW0.as_up_tuser;
			force dut.AXIS_SW0.up_as_tlast =  dut.AXIS_SW0.as_up_tlast;

		
		end
	endtas

[code link](https://github.com/TonyHo722/fsic_tony/blob/main/dsn/testbench/tb_fsic.v#L1398C1-L1413C8)

# update FPGA_to_SOC_UP_BASE
- please use FPGA_to_SOC_UP_BASE to access user project axilite register from FPGA.
[update in this commit](https://github.com/TonyHo722/fsic_tony/commit/051b3859a41ef956c2e56feaa4ac5898e62104f6)