# found issue in systemverilog code when running make verify-system_test111-rtl for FSIC tape-out flow.

- Error log

1. event triggerd issue
system_test111_tb.v:850: error: Event name soc_to_fpga_axilite_read_cpl_event can't have member names (triggered)
system_test111_tb.v:850: internal error: incomprehensible wait expression width (0).
system_test111_tb.v:983: error: Event name soc_to_fpga_mailbox_write_event can't have member names (triggered)
system_test111_tb.v:983: internal error: incomprehensible wait expression width (0).
2. assignment issue
axi_ctrl_logic.sv:311: error: This assignment requires an explicit cast.

reference this [commit](https://github.com/TonyHo722/caravel_user_project/commit/c5ce732e583763075a9549afbf06882f60f7f84f) for patch.

# using a sample code to repro iverilog complier issue in using event_a.triggered

tb.sv:10: error: Unable to bind wire/reg/memory `event_a.triggered' in `tb'
tb.sv:10: error: Unable to elaborate wait condition expression.

[commit of systemverilog_study](https://github.com/TonyHo722/systemverilog_study/commit/a8b3dfac60a429bef175ba6e1e160ab506515239)

- code

      begin
        wait(event_a.triggered);
        $display ("[%0t] Thread1: Wait for event_a is over", $time);
      end

- using xvlog comipler is ok in [xvlog.log](https://github.com/TonyHo722/systemverilog_study/blob/a8b3dfac60a429bef175ba6e1e160ab506515239/systemverilog_event/xvlog.log)

## iverilog issue is fixed by [update code to patch iverilog report error](https://github.com/TonyHo722/systemverilog_study/commit/ac4491821920b64d17b3ee94cb61c43e1a4c5e8f) and [using @ for event](https://github.com/TonyHo722/systemverilog_study/commit/83909aaeb714f810b397c4c0cf5cb1a96fac2aba)