FSIC ASIC Integration & Implementation Status - 20230918

# caravel-lab for fsic
- after hack some design in AA, AS and testbench then fsic run openlane flow pass.
- pass log
- [run_fsic.log](https://github.com/TonyHo722/caravel-lab/blob/1b96607802059099ac4f781af9638077d97069a4/bash_auto/ubuntu5/run_fsic.log)

Successfully remade target file 'run-precheck'.

## [build fsic in caravel-lab issue when no user_proj_example](https://hackmd.io/@TonyHo/HJoS_Nrk6)

- pass

user_project_wrapper -> user_proj_example -> fsic

- fail

user_project_wrapper -> fsic

# latch issue
## in axis_switch
- hurry fixed it by update code
## in axis_axil
- TBD

# ERROR: Multiple edge sensitive events found for this signal!
## in io_serdes
[fixed run yosys issue - ERROR: Multiple edge sensitive events found for this signal!](https://hackmd.io/@TonyHo/rJLieq603)
## in axis_switch
- hurry found solution
## in axis_axil
- TBD

# wait(uut.mprj.u_fsic.U_IO_SERDES0.rxen) issue in synthesys
- I want to wait a internal signal of fsic in testbench, but synthesys will change the hierarchy
- error in using （* keep_hierarchy = “yes” *）
- I will try to use delay in testbench to replace wait.

## error in using （* keep_hierarchy = “yes” *）
- [use "DONT TOUCH" issue in run_fsic](https://hackmd.io/@TonyHo/HJ685pQy6)
- error message

    [INFO]: Running Synthesis (log: ../SSD1T/debug/fsic_0913debug_fsic_onefile/caravel_user_project/openlane/user_proj_example/runs/23_09_17_11_05/logs/synthesis/1-synthesis.log)...
    [ERROR]: during executing yosys script /openlane/scripts/yosys/synth.tcl
    [ERROR]: Log: ../SSD1T/debug/fsic_0913debug_fsic_onefile/caravel_user_project/openlane/user_proj_example/runs/23_09_17_11_05/logs/synthesis/1-synthesis.log
    [ERROR]: Last 10 lines:
    Used module:     \FSIC
    Used module:         \FSIC_CLKRST
    Used module:         \AXIS_SW
    Used module:         \AXIL_AXIS
    Used module:         \CFG_CTRL
    Parameter \BITS = 32
    
    4.2. Executing AST frontend in derive mode using pre-parsed AST for module `\FSIC'.
    ERROR: Module `\MPRJ_IO' referenced in module `\FSIC' in cell `\U_MPRJ_IO0' is not part of the design.
    child process exited abnormally
    
    [ERROR]: Creating issue reproducible...

# Question
## How to set constrain in io_clk in config.json?

[config.json](https://github.com/TonyHo722/caravel-lab/blob/1b96607802059099ac4f781af9638077d97069a4/custom_design/fsic/openlane/user_proj_example/config.json#L6C1-L7C34)

    "DESIGN_NAME": "user_proj_example",
    "DESIGN_IS_CORE": 0,
    "VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", "dir::../../verilog/rtl/user_proj_example.v" ],
    "CLOCK_PERIOD": 85,
    "CLOCK_PORT": "wb_clk_i",
    "CLOCK_NET": "u_fsic.wb_clk",
    "FP_SIZING": "absolute",

[user_proj_example.v](https://github.com/TonyHo722/caravel-lab/blob/1b96607802059099ac4f781af9638077d97069a4/custom_design/fsic/verify-fsic-rtl/user_proj_example.v)

module user_proj_example #(
    parameter BITS = 32
)(
	...
    input wb_clk_i,
	...
    // IOs
    input  [`MPRJ_IO_PADS-1:0] io_in,
    output [`MPRJ_IO_PADS-1:0] io_out,
    output [`MPRJ_IO_PADS-1:0] io_oeb,	
	...	
	);
	
	...
	FSIC #(.BITS( BITS )) u_fsic  (
		...
        .wb_clk      (wb_clk_i),                // I	
		...
        // IO Pads
        .io_in       (io_in),                   // I  38
        .io_out      (io_out),                  // O  38
        .io_oeb      (io_oeb),                  // O  38		
		...
	);
endmodule