use SYNTH_STRATEGY in config.json to fix [STEP 14] ANTENNA issue

# example for run docker in manual mode - reference - [OpenLane Overview - Youtube](https://www.youtube.com/watch?v=d0hPdkYg5QI) - [configuration.md](https://github.com/The-OpenROAD-Project/OpenLane/blob/6ab36bf20edfd4d111b7a59b21f4050622a03f5a/docs/source/reference/configuration.md) - [openlane document](https://github.com/The-OpenROAD-Project/OpenLane/tree/6ab36bf20edfd4d111b7a59b21f4050622a03f5a/docs) ## step 1. get the docker command from run_fsic.log - search by `vimgrep 'docker run -it -v' %` in vi - it should be match 2 items as below - user_proj_example - user_project_wrapper ``` docker run -it -v $(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..):$(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..) -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/openlane_src:/openlane -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -e PDK_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -e PDK=sky130A -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -e OPENLANE_RUN_TAG=23_10_05_17_27 -e MCW_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -u 1000:1000 \ efabless/openlane:2022.11.19 sh -c "flow.tcl -design $(realpath ./user_proj_example) -save_path $(realpath ..) -save -tag 23_10_05_17_27 -overwrite -ignore_mismatches" ``` [log link](https://github.com/TonyHo722/caravel-lab/blob/a4de87787e71b828ea96f0d8223081a06b54e196/bash_auto/ubuntu5/run_fsic.log#L1057C1-L1059C1) - in ubuntu5 machine the folder in below /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/ ## step 2. update docker command then execution - command ``` docker run -it -v $(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..):$(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..) -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/openlane_src:/openlane -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -e PDK_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -e PDK=sky130A -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -e OPENLANE_RUN_TAG=23_10_05_17_27 -e MCW_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -u 1000:1000 \ efabless/openlane:2022.11.19 ``` - result ``` (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq$ docker run -it -v $(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..):$(realpath /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/..) -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/openlane_src:/openlane -v /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -e PDK_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks -e PDK=sky130A -e MISMATCHES_OK=1 -e CARAVEL_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/caravel -e OPENLANE_RUN_TAG=23_10_05_17_27 -e MCW_ROOT=/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/mgmt_core_wrapper -u 1000:1000 \ > efabless/openlane:2022.11.19 OpenLane Container (cb59d1f):/openlane$ ``` - in step 2, it create a docker container named cranky_hermann show in step 3 ## step 3. check docker container in other terminal - the docker container name is cranky_hermann is created by step 2 ``` $ docker ps CONTAINER ID IMAGE COMMAND CREATED STATUS PORTS NAMES f41386224c9b efabless/openlane:2022.11.19 "/bin/sh -c /bin/bash" 10 seconds ago Up 9 seconds cranky_hermann ``` ## step 4. execution flow.tcl in docker for synth_explore with -tag synth_explore_test - command ``` ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag synth_explore_test -overwrite -ignore_mismatches -synth_explore ``` - result ``` OpenLane Container (cb59d1f):/openlane$ ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag synth_explore_test -overwrite -ignore_mismatches -synth_explore OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 All rights reserved. (c) 2020-2022 Efabless Corporation and contributors. Available under the Apache License, version 2.0. See the LICENSE file for more details. [WARNING]: OpenLane may not function properly: The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c) This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`. [INFO]: Using configuration in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/config.json'... [INFO]: PDK Root: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks [INFO]: Process Design Kit: sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd [INFO]: Run Directory: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/synth_explore_test [INFO]: Preparing LEF files for the nom corner... [INFO]: Preparing LEF files for the min corner... [INFO]: Preparing LEF files for the max corner... [INFO]: Running Synthesis Exploration... [INFO]: This is a Synthesis Exploration and so no need to remove the defparam lines. [INFO]: Generating exploration report... [SUCCESS]: Done with synthesis exploration: See report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/synth_explore_test/reports/synthesis/0-exploration_analysis.html'. OpenLane Container (cb59d1f):/openlane$ ``` - html file in /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/synth_explore_test/reports/synthesis/0-exploration_analysis.html ## step 5. use web browser to check the result ![](https://hackmd.io/_uploads/SJw4rj_za.png) ## step 6. update config.json with SYNTH_STRATEGY = AREA 3 ``` (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example$ vi config.json ``` - add below config setting ``` "SYNTH_STRATEGY": "AREA 3", ``` ![](https://hackmd.io/_uploads/HJI9HjdGa.png) ## step 7. execution flow.tcl in docker after update config.json with -tag 1027_debug - command ``` ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag 1027_debug -overwrite -ignore_mismatches ``` - result summary - the [STEP 14] ANTENNA issue is fixed by update configuration "SYNTH_STRATEGY = AREA 3" - still with hold time voilate issue - detail log ``` OpenLane Container (cb59d1f):/openlane$ ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag 1027_debug -overwrite -ignore_mismatches OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 All rights reserved. (c) 2020-2022 Efabless Corporation and contributors. Available under the Apache License, version 2.0. See the LICENSE file for more details. [WARNING]: OpenLane may not function properly: The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c) This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`. [INFO]: Using configuration in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/config.json'... [INFO]: PDK Root: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks [INFO]: Process Design Kit: sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd [INFO]: Run Directory: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug [INFO]: Preparing LEF files for the nom corner... [INFO]: Preparing LEF files for the min corner... [INFO]: Preparing LEF files for the max corner... [STEP 1] [INFO]: Running Synthesis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/synthesis/1-synthesis.log)... [STEP 2] [INFO]: Running Single-Corner Static Timing Analysis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/synthesis/2-sta.log)... [STEP 3] [INFO]: Running Initial Floorplanning (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/floorplan/3-initial_fp.log)... [INFO]: Floorplanned with width 888.72 and height 576.64. [STEP 4] [INFO]: Running IO Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/floorplan/4-place_io.log)... [STEP 5] [INFO]: Running Tap/Decap Insertion (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/floorplan/5-tap.log)... [INFO]: Power planning with power {vccd1} and ground {vssd1}... [STEP 6] [INFO]: Generating PDN (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/floorplan/6-pdn.log)... [STEP 7] [INFO]: Running Global Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/placement/7-global.log)... [STEP 8] [INFO]: Running Placement Resizer Design Optimizations (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/placement/8-resizer.log)... [STEP 9] [INFO]: Running Detailed Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/placement/9-detailed.log)... [STEP 10] [INFO]: Running Clock Tree Synthesis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/cts/10-cts.log)... [STEP 11] [INFO]: Running Placement Resizer Timing Optimizations (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/cts/11-resizer.log)... [STEP 12] [INFO]: Running Global Routing Resizer Timing Optimizations (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/12-resizer.log)... [STEP 13] [INFO]: Running Diode Insertion (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/13-diodes.log)... [STEP 14] [INFO]: Running Detailed Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/14-diode_legalization.log)... [STEP 15] [INFO]: Running Fill Insertion (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/15-fill.log)... [STEP 16] [INFO]: Running Global Routing (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/16-global.log)... [STEP 17] [INFO]: Writing Verilog (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/16-global_write_netlist.log)... [STEP 18] [INFO]: Running Detailed Routing (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/18-detailed.log)... [INFO]: No DRC violations after detailed routing. [STEP 19] [INFO]: Checking Wire Lengths (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/routing/19-wire_lengths.log)... [STEP 20] [INFO]: Running SPEF Extraction at the min process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/20-parasitics_extraction.min.log)... [STEP 21] [INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/21-rcx_mcsta.min.log)... [STEP 22] [INFO]: Running SPEF Extraction at the max process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/22-parasitics_extraction.max.log)... [STEP 23] [INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/23-rcx_mcsta.max.log)... [STEP 24] [INFO]: Running SPEF Extraction at the nom process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/24-parasitics_extraction.nom.log)... [STEP 25] [INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/25-rcx_mcsta.nom.log)... [STEP 26] [INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/26-rcx_sta.log)... [STEP 27] [INFO]: Creating IR Drop Report (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/27-irdrop.log)... [STEP 28] [INFO]: Running Magic to generate various views... [INFO]: Streaming out GDSII with Magic (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/28-gdsii.log)... [INFO]: Generating MAGLEF views... [STEP 29] [INFO]: Streaming out GDSII with KLayout (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/29-gdsii-klayout.log)... [STEP 30] [INFO]: Running XOR on the layouts using KLayout (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/30-xor.log)... [STEP 31] [INFO]: Running Magic Spice Export from LEF (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/31-spice.log)... [STEP 32] [INFO]: Writing Powered Verilog (logs: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/32-write_powered_def.log, ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/32-write_powered_verilog.log)... [STEP 33] [INFO]: Writing Verilog (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/32-write_powered_verilog.log)... [STEP 34] [INFO]: Running LVS (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/34-lvs.lef.log)... [STEP 35] [INFO]: Running Magic DRC (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/35-drc.log)... [INFO]: Converting Magic DRC database to various tool-readable formats... [INFO]: No DRC violations after GDS streaming out. [STEP 36] [INFO]: Running OpenROAD Antenna Rule Checker (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/logs/signoff/36-antenna.log)... [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/results/final'... [INFO]: Saving runtime environment... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/metrics.csv'. [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/signoff/26-rcx_sta.slew.rpt'. [ERROR]: There are hold violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/signoff/26-rcx_sta.min.rpt'. [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/results/final'... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/metrics.csv'. [INFO]: Saving runtime environment... [ERROR]: Flow failed. [INFO]: The failure may have been because of the following warnings: [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/signoff/26-rcx_sta.slew.rpt'. OpenLane Container (cb59d1f):/openlane$ ``` ## step 8. exit docker ``` OpenLane Container (cb59d1f):/openlane$ exit exit (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq$ ``` ## step 9 to 13 is for 2nd run docker from a container - step 1 to 8 is run docker from a docker image (efabless/openlane:2022.11.19), it create a docker container named cranky_hermann in step 2 - step 9 to 13 using cranky_hermann and update config.json file to debug different configuration setting config.json ## step 9. docker ps -a - docker container name = cranky_hermann ``` (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq$ docker ps -a | more CONTAINER ID IMAGE COMMAND CREATED STATUS PORTS NAMES f41386224c9b efabless/openlane:2022.11.19 "/bin/sh -c /bin/bash" 54 minutes ago Exited (0) About a minute ago cranky_hermann ``` ## step 10. start docker container - command ``` docker start cranky_hermann ``` - result ``` (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq$ docker start cranky_hermann cranky_hermann ``` - use docker ps to check it - it is running ``` (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq$ docker ps CONTAINER ID IMAGE COMMAND CREATED STATUS PORTS NAMES f41386224c9b efabless/openlane:2022.11.19 "/bin/sh -c /bin/bash" 56 minutes ago Up 27 seconds cranky_hermann 1f125f8e25a7 efabless/openlane:7a633af3dee06a65019cb82301db4e25d08339f5-amd64 "/bin/sh -c /bin/bash" 45 hours ago Up 45 hours naughty_torvalds db4548c38f7b efabless/openlane:2022.11.19 "/bin/sh -c /bin/bash" 2 weeks ago Up 2 weeks romantic_lovelace (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq$ ``` ## step 11. exec docker container - command ``` docker exec -it cranky_hermann bash ``` - result ``` (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq$ docker exec -it cranky_hermann bash OpenLane Container (cb59d1f):/openlane$ ``` ## step 12. update config.json - command ``` (base) tonyho@ubuntu5:/ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example$ vi config.json ``` - modify as below ``` "CLOCK_PORT": "io_in[37]", "CLOCK_NET": "io_in[37]", ``` ## step 13. execution flow.tcl in docker after update config.json with -tag 1027_debug_clock_4 - command ``` ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag 1027_debug_clock_4 -overwrite -ignore_mismatches ``` - result : pass ``` OpenLane Container (cb59d1f):/openlane$ ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag 1027_debug_clock_4 -overwrite -ignore_mismatches OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 All rights reserved. (c) 2020-2022 Efabless Corporation and contributors. Available under the Apache License, version 2.0. See the LICENSE file for more details. [WARNING]: OpenLane may not function properly: The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c) This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`. [INFO]: Using configuration in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/config.json'... [INFO]: PDK Root: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks [INFO]: Process Design Kit: sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd [INFO]: Run Directory: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4 [INFO]: Preparing LEF files for the nom corner... [INFO]: Preparing LEF files for the min corner... [INFO]: Preparing LEF files for the max corner... [STEP 1] [INFO]: Running Synthesis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/synthesis/1-synthesis.log)... [STEP 2] [INFO]: Running Single-Corner Static Timing Analysis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/synthesis/2-sta.log)... [STEP 3] [INFO]: Running Initial Floorplanning (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/floorplan/3-initial_fp.log)... [INFO]: Floorplanned with width 888.72 and height 576.64. [STEP 4] [INFO]: Running IO Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/floorplan/4-place_io.log)... [STEP 5] [INFO]: Running Tap/Decap Insertion (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/floorplan/5-tap.log)... [INFO]: Power planning with power {vccd1} and ground {vssd1}... [STEP 6] [INFO]: Generating PDN (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/floorplan/6-pdn.log)... [STEP 7] [INFO]: Running Global Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/placement/7-global.log)... [STEP 8] [INFO]: Running Placement Resizer Design Optimizations (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/placement/8-resizer.log)... [STEP 9] [INFO]: Running Detailed Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/placement/9-detailed.log)... [STEP 10] [INFO]: Running Clock Tree Synthesis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/cts/10-cts.log)... [STEP 11] [INFO]: Running Placement Resizer Timing Optimizations (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/cts/11-resizer.log)... [STEP 12] [INFO]: Running Global Routing Resizer Timing Optimizations (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/12-resizer.log)... [STEP 13] [INFO]: Running Diode Insertion (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/13-diodes.log)... [STEP 14] [INFO]: Running Detailed Placement (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/14-diode_legalization.log)... [STEP 15] [INFO]: Running Fill Insertion (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/15-fill.log)... [STEP 16] [INFO]: Running Global Routing (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/16-global.log)... [STEP 17] [INFO]: Writing Verilog (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/16-global_write_netlist.log)... [STEP 18] [INFO]: Running Detailed Routing (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/18-detailed.log)... [INFO]: No DRC violations after detailed routing. [STEP 19] [INFO]: Checking Wire Lengths (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/routing/19-wire_lengths.log)... [STEP 20] [INFO]: Running SPEF Extraction at the min process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/20-parasitics_extraction.min.log)... [STEP 21] [INFO]: Running Multi-Corner Static Timing Analysis at the min process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/21-rcx_mcsta.min.log)... [STEP 22] [INFO]: Running SPEF Extraction at the max process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/22-parasitics_extraction.max.log)... [STEP 23] [INFO]: Running Multi-Corner Static Timing Analysis at the max process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/23-rcx_mcsta.max.log)... [STEP 24] [INFO]: Running SPEF Extraction at the nom process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/24-parasitics_extraction.nom.log)... [STEP 25] [INFO]: Running Multi-Corner Static Timing Analysis at the nom process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/25-rcx_mcsta.nom.log)... [STEP 26] [INFO]: Running Single-Corner Static Timing Analysis at the nom process corner (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/26-rcx_sta.log)... [STEP 27] [INFO]: Creating IR Drop Report (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/27-irdrop.log)... [STEP 28] [INFO]: Running Magic to generate various views... [INFO]: Streaming out GDSII with Magic (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/28-gdsii.log)... [INFO]: Generating MAGLEF views... [STEP 29] [INFO]: Streaming out GDSII with KLayout (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/29-gdsii-klayout.log)... [STEP 30] [INFO]: Running XOR on the layouts using KLayout (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/30-xor.log)... [STEP 31] [INFO]: Running Magic Spice Export from LEF (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/31-spice.log)... [STEP 32] [INFO]: Writing Powered Verilog (logs: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/32-write_powered_def.log, ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/32-write_powered_verilog.log)... [STEP 33] [INFO]: Writing Verilog (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/32-write_powered_verilog.log)... [STEP 34] [INFO]: Running LVS (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/34-lvs.lef.log)... [STEP 35] [INFO]: Running Magic DRC (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/35-drc.log)... [INFO]: Converting Magic DRC database to various tool-readable formats... [INFO]: No DRC violations after GDS streaming out. [STEP 36] [INFO]: Running OpenROAD Antenna Rule Checker (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/logs/signoff/36-antenna.log)... [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/results/final'... [INFO]: Saving runtime environment... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/reports/metrics.csv'. [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/reports/signoff/26-rcx_sta.slew.rpt'. [INFO]: There are no hold violations in the design at the typical corner. [INFO]: There are no setup violations in the design at the typical corner. [SUCCESS]: Flow complete. [INFO]: Note that the following warnings have been generated: [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/reports/signoff/26-rcx_sta.slew.rpt'. OpenLane Container (cb59d1f):/openlane$ ``` # issue : how to config 2 clocks in config.json? - fsic with two clocks - wb_clk for core_clock in fsic - io_in[37] for io_clock ## config.json.org with -tag 1027_debug ``` "CLOCK_PORT": "wb_clk_i", "CLOCK_NET": "u_fsic.wb_clk", "SYNTH_STRATEGY": "AREA 3", ``` - log ``` [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/signoff/26-rcx_sta.slew.rpt'. [ERROR]: There are hold violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/signoff/26-rcx_sta.min.rpt'. [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/results/final'... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/metrics.csv'. [INFO]: Saving runtime environment... [ERROR]: Flow failed. [INFO]: The failure may have been because of the following warnings: [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug/reports/signoff/26-rcx_sta.slew.rpt'. ``` ## config.json.1027_debug_clock.pass with -tag 1027_debug_clock ``` "CLOCK_PORT": "wb_clk_i", "CLOCK_NET": "u_fsic.wb_clk", "CLOCK_PORT": "io_in[37]", "CLOCK_NET": "io_in[37]", "SYNTH_STRATEGY": "AREA 3", "FP_SIZING": "absolute", ``` - pass log ``` [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock/reports/signoff/26-rcx_sta.slew.rpt'. [INFO]: There are no hold violations in the design at the typical corner. [INFO]: There are no setup violations in the design at the typical corner. [SUCCESS]: Flow complete. [INFO]: Note that the following warnings have been generated: [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock/reports/signoff/26-rcx_sta.slew.rpt'. ``` ## config.json.1027_debug_clock_2.bad with -tag 1027_debug_clock_2 ``` "CLOCK_PORT": ["wb_clk_i", "io_in[37]"], "CLOCK_NET": ["u_fsic.wb_clk", "io_in[37]"], "SYNTH_STRATEGY": "AREA 3", ``` - error log ``` [ERROR]: during executing openroad script /openlane/scripts/openroad/floorplan.tcl [ERROR]: Log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/logs/floorplan/3-initial_fp.log [ERROR]: Last 10 lines: To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/tmp/merged.nom.lef at line 68342. [INFO ODB-0223] Created 13 technology layers [INFO ODB-0224] Created 25 technology vias [INFO ODB-0225] Created 441 library cells [INFO ODB-0226] Finished LEF file: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/tmp/merged.nom.lef Reading netlist... [ERROR STA-0408] create_clock requires zero or one positional arguments. Error: 3-initial_fp.sdc, 11 STA-0408 child process exited abnormally [ERROR]: Creating issue reproducible... ``` - detail log ``` OpenLane Container (cb59d1f):/openlane$ ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag 1027_debug_clock_2 -overwrite -ignore_mismatches OpenLane cb59d1f84deb5cedbb5b0a3e3f3b4129a967c988 All rights reserved. (c) 2020-2022 Efabless Corporation and contributors. Available under the Apache License, version 2.0. See the LICENSE file for more details. [WARNING]: OpenLane may not function properly: The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c) This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`. [INFO]: Using configuration in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/config.json'... [INFO]: PDK Root: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/dependencies/pdks [INFO]: Process Design Kit: sky130A [INFO]: Standard Cell Library: sky130_fd_sc_hd [INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd [INFO]: Run Directory: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2 [INFO]: Preparing LEF files for the nom corner... [INFO]: Preparing LEF files for the min corner... [INFO]: Preparing LEF files for the max corner... [STEP 1] [INFO]: Running Synthesis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/logs/synthesis/1-synthesis.log)... [STEP 2] [INFO]: Running Single-Corner Static Timing Analysis (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/logs/synthesis/2-sta.log)... [STEP 3] [INFO]: Running Initial Floorplanning (log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/logs/floorplan/3-initial_fp.log)... [ERROR]: during executing openroad script /openlane/scripts/openroad/floorplan.tcl [ERROR]: Log: ../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/logs/floorplan/3-initial_fp.log [ERROR]: Last 10 lines: To avoid this warning in the future, remove this statement from the LEF file with version 5.6 or later. See file /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/tmp/merged.nom.lef at line 68342. [INFO ODB-0223] Created 13 technology layers [INFO ODB-0224] Created 25 technology vias [INFO ODB-0225] Created 441 library cells [INFO ODB-0226] Finished LEF file: /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/tmp/merged.nom.lef Reading netlist... [ERROR STA-0408] create_clock requires zero or one positional arguments. Error: 3-initial_fp.sdc, 11 STA-0408 child process exited abnormally [ERROR]: Creating issue reproducible... [INFO]: Saving runtime environment... OpenLane TCL Issue Packager EFABLESS CORPORATION AND ALL AUTHORS OF THE OPENLANE PROJECT SHALL NOT BE HELD LIABLE FOR ANY LEAKS THAT MAY OCCUR TO ANY PROPRIETARY DATA AS A RESULT OF USING THIS SCRIPT. THIS SCRIPT IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND. BY USING THIS SCRIPT, YOU ACKNOWLEDGE THAT YOU FULLY UNDERSTAND THIS DISCLAIMER AND ALL IT ENTAILS. Parsing config file(s)… Setting up /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/issue_reproducible… Done. [INFO]: Reproducible packaged: Please tarball and upload '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/issue_reproducible' if you're going to submit an issue. [INFO]: Saving current set of views in '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/results/final'... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_2/reports/metrics.csv'. [INFO]: Saving runtime environment... [ERROR]: Flow failed. ``` ## config.json.1027_debug_clock_3.pass with -tag 1027_debug_clock_3 ``` "CLOCK_PORT": ["io_in[37]"], "CLOCK_NET": ["io_in[37]"], "SYNTH_STRATEGY": "AREA 3", ``` - pass log ``` [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_3/reports/signoff/26-rcx_sta.slew.rpt'. [INFO]: There are no hold violations in the design at the typical corner. [INFO]: There are no setup violations in the design at the typical corner. [SUCCESS]: Flow complete. [INFO]: Note that the following warnings have been generated: [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_3/reports/signoff/26-rcx_sta.slew.rpt'. ``` ## config.json.1027_debug_clock_4.pass with -tag 1027_debug_clock_4 ``` "CLOCK_PORT": "io_in[37]", "CLOCK_NET": "io_in[37]", "SYNTH_STRATEGY": "AREA 3", ``` - pass log ``` [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/reports/signoff/26-rcx_sta.slew.rpt'. [INFO]: There are no hold violations in the design at the typical corner. [INFO]: There are no setup violations in the design at the typical corner. [SUCCESS]: Flow complete. [INFO]: Note that the following warnings have been generated: [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_4/reports/signoff/26-rcx_sta.slew.rpt'. ``` ## config.json.1027_debug_clock_5.pass with -tag 1027_debug_clock_5 ``` "CLOCK_PORT": "io_in[37]", "CLOCK_NET": "io_in[37]", "//SYNTH_STRATEGY": "AREA 3", ``` - pass log ``` [WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_5/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_5/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_5/reports/signoff/26-rcx_sta.slew.rpt'. [INFO]: There are no hold violations in the design at the typical corner. [INFO]: There are no setup violations in the design at the typical corner. [SUCCESS]: Flow complete. [INFO]: Note that the following warnings have been generated: [WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_5/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_5/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example/runs/1027_debug_clock_5/reports/signoff/26-rcx_sta.slew.rpt'. ``` # synth_explore with -tag synth_explore_test_clock_changed - use config.json.1027_debug_clock_5.pass - command ``` ./flow.tcl -design /ADATA2T/debug/fsic_1005_merge_verify_rtl_irq/caravel_user_project/openlane/user_proj_example -tag synth_explore_test_clock_changed -overwrite -ignore_mismatches -synth_explore ``` # question how to manaual control [STEP 1] synthesis?