# issue : Warning: The following end-points are not constrained for maximum delay.

- check_timing warning

Information: Checking unconstrained_endpoints...

Warning: The following end-points are not constrained for maximum delay.

End point
---------------
mprj/u_fsic/U_AXIL_AXIS0/axi_ctrl_logic/data_ss_reg[0]/D

- gl

  SAEDRVT14_LDPQ_1 \data_ss_reg[0]  ( .G(n258), .D(N666), .Q(data_ss[0]) );



- code

    always_latch begin


        if(axi_state == AXI_DECIDE_DEST)begin
            case(next_trans)
                TRANS_LS: begin // request come from left side - axilite_slave
                    case(trans_typ)
                        AXI_WR: begin
                        	...
                        end
                        AXI_RD: begin
                        	...
                        end
                    endcase
                end
                TRANS_SS: begin // request come from right side - axis_slave
                    case(first_ss_tuser)
                        2'b01: begin // axis slave two-cycle data with tuser = 2'b01, can be converted to axilite write address / write data
                            ...
                            if(secnd_data_ss_valid)begin
                                ...
                                data_ss = secnd_data_ss;
                                ...
                            end
                        end
                        2'b10: begin // axis slave one-cycle data with tuser = 2'b10, can be converted to axilite read address
                            ...
                        end
                        2'b11: begin // read user project wrapper, data go back from CC through axis
                            data_ss = first_ss_tdata;
                            ...
                        end
                    endcase
                end
            endcase
        end
        else begin
            ...
            data_ss = 32'b0;
            ...
        end
    end

[code link](https://github.com/bol-edu/fsic_fpga/blob/main/rtl/user/axilite_axis/rtl/axi_ctrl_logic.sv#L418)