# History
20240207 update final solution
- update verilog code - create a MUX instance from MUX in EDK lib and set dont_touch then synthesis tool keep this MUX instance for source_object of create_generated_clock

# Summmary
## issue 1: MUX output pin name(cell name) is changed after compile
- When the source_objects of create_generated_clock is a MUX output pin
- The MUX output pin name is changed after compile.
- I suspect the MUX cell is GETCH type and after compile, the MUX cell is mapping to target library. It means the MUX output pin always changed after compile.
- how to provide MUX output pin name in sdc file?
- [workaround] create_generated_clock & compile 2nd times for patch MUX output pin name(cell name) changed issue

## issue 2: timing false path issue
- fixed by set_false_path

# reference log files
[0201_008](https://drive.google.com/drive/folders/1Mfiyhx_F1f1qJECe_E4BwycMjlu1_FOI?usp=drive_link)

# issue 1 : MUX output pin name is changed after compile
## code

    assign csclk = (wbbd_busy) ? wbbd_sck : ((spi_is_active) ? mgmt_gpio_in[4] : 1'b0);

[code link](https://github.com/TonyHo722/caravel-lite/blob/23f2329117ba2744620bd83f7526cb2b876aef67/verilog/rtl/housekeeping.v#L1037C1-L1037C88)

## sdc file
set clk_period 20
create_clock -name clk -period $clk_period [get_ports {clock}]

create_clock -name hkspi_clk -period 100 [get_ports {mprj_io[4]} ]

set wbbd_sck_pin [get_pins -of_objects housekeeping/wbbd_sck -filter lib_pin_name==Q]

create_generated_clock -name wbbd_sck -source [get_ports {housekeeping/wb_clk_i} ] -divide_by 2 $wbbd_sck_pin

source $wbbd_sck_pin -divide_by 1 [get_pins housekeeping/C13888/Z_0]
create_generated_clock -name wbbd_sck_to_csclk_mux -source [get_ports clock] -divide_by 2 [get_pins housekeeping/C13888/Z_0]

create_generated_clock -name hkspi_clk_to_csclk_mux -source [get_ports {mprj_io[4]}] -add -divide_by 1 [get_pins housekeeping/C13888/Z_0]

set_clock_groups -logically_exclusive -name csclk_mux -group wbbd_sck_to_csclk_mux -group hkspi_clk_to_csclk_mux

## MUX cell name and output pin name before compiler


## run tcl file log

all_connected housekeeping/csclk
{housekeeping/C13888/Z_0 housekeeping/hkspi_disable_reg/clocked_on 
...
housekeeping/gpio_configure_reg[34][5]/clocked_on ...}

compile -exact_map -map_effort high -area_effort medium -power_effort none


Warning: The source of the generated clock 'wbbd_sck_to_csclk_mux' is not known. Ignoring generated_clock 'wbbd_sck_to_csclk_mux'. (TIM-018)
Warning: The source of the generated clock 'hkspi_clk_to_csclk_mux' is not known. Ignoring generated_clock 'hkspi_clk_to_csclk_mux'. (TIM-018)
Warning: 'set_clock_group' constraint made a reference 'group wbbd_sck_to_csclk_mux' which no longer exists.  (TIM-179)
Warning: 'set_clock_group' constraint made a reference 'group hkspi_clk_to_csclk_mux' which no longer exists.  (TIM-179)
Warning: This 'set_clock_group' constraint is no longer applicable to any path. (TIM-178)

all_connected housekeeping/csclk

{housekeeping/U4731/X housekeeping/mgmt_gpio_data_reg[10]/CK 
...
housekeeping/gpio_configure_reg[36][6]/CK ...}

## Warning: The source of the generated clock 'wbbd_sck_to_csclk_mux' is not known
- Warning message during compile

## MUX cell name and output pin name after compiler


## workaround
- update create_generated_clock after compile

all_connected housekeeping/csclk
compile -exact_map -map_effort high -area_effort medium -power_effort none

Warning: The source of the generated clock 'wbbd_sck_to_csclk_mux' is not known. Ignoring generated_clock 'wbbd_sck_to_csclk_mux'. (TIM-018)
Warning: The source of the generated clock 'hkspi_clk_to_csclk_mux' is not known. Ignoring generated_clock 'hkspi_clk_to_csclk_mux'. (TIM-018)
Warning: 'set_clock_group' constraint made a reference 'group wbbd_sck_to_csclk_mux' which no longer exists.  (TIM-179)
Warning: 'set_clock_group' constraint made a reference 'group hkspi_clk_to_csclk_mux' which no longer exists.  (TIM-179)
Warning: This 'set_clock_group' constraint is no longer applicable to any path. (TIM-178)


create_generated_clock -name wbbd_sck_to_csclk_mux -source  [get_ports clock] -divide_by 2 [get_pins housekeeping/U4718/X]
create_generated_clock -name hkspi_clk_to_csclk_mux -source [get_ports {mprj_io[4]}] -add -divide_by 1 [get_pins housekeeping/U4718/X]
set_clock_groups -logically_exclusive -name csclk_mux -group wbbd_sck_to_csclk_mux -group hkspi_clk_to_csclk_mux 
all_connected housekeeping/csclk

compile -exact_map -map_effort high -area_effort medium -power_effort none

all_connected housekeeping/csclk

### after workaround - found timing false path issue in report_timing
- clk -> hkspi_clk_to_csclk_mux
- hkspi_clk -> wbbd_sck_to_csclk_mux

dc_shell> report_timing -to housekeeping/pll_sel_reg[0]/D

****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : caravel_top
Version: U-2022.12
Date   : Wed Jan 31 21:22:14 2024
****************************************

 # A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: tt0p8v25c   Library: saed14rvt_tt0p8v25c
Wire Load Model Mode: top

  Startpoint: housekeeping/wbbd_busy_reg
              (rising edge-triggered flip-flop clocked by clk)
  Endpoint: housekeeping/pll_sel_reg[0]
            (rising edge-triggered flip-flop clocked by hkspi_clk_to_csclk_mux)
  Path Group: hkspi_clk_to_csclk_mux
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                  80.00      80.00
  clock network delay (ideal)                             0.00      80.00
  housekeeping/wbbd_busy_reg/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00      80.00 r
  housekeeping/wbbd_busy_reg/Q (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.02      80.02 r
  housekeeping/U3742/X (SAEDRVT14_BUF_S_1)                0.02      80.04 r
  housekeeping/U2365/X (SAEDRVT14_INV_1)                  0.01      80.05 f
  housekeeping/U1249/X (SAEDRVT14_BUF_S_1)                0.02      80.07 f
  housekeeping/U2837/X (SAEDRVT14_NR2_MM_1)               0.01      80.08 r
  housekeeping/U3607/X (SAEDRVT14_AO21_1)                 0.01      80.09 r
  housekeeping/U1681/X (SAEDRVT14_OAI21_0P75)             0.04      80.13 f
  housekeeping/U1071/X (SAEDRVT14_BUF_S_1)                0.02      80.15 f
  housekeeping/U527/X (SAEDRVT14_INV_1)                   0.01      80.16 r
  housekeeping/U301/X (SAEDRVT14_BUF_S_1)                 0.01      80.17 r
  housekeeping/U311/X (SAEDRVT14_BUF_S_1)                 0.01      80.19 r
  housekeeping/U174/X (SAEDRVT14_ND2_CDC_1)               0.02      80.20 f
  housekeeping/U96/X (SAEDRVT14_INV_1)                    0.01      80.22 r
  housekeeping/U3686/X (SAEDRVT14_OAI22_1)                0.01      80.22 f
  housekeeping/pll_sel_reg[0]/D (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00      80.22 f
  data arrival time                                                 80.22

  clock hkspi_clk_to_csclk_mux (rise edge)              100.00     100.00
  clock network delay (ideal)                             0.00     100.00
  housekeeping/pll_sel_reg[0]/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00     100.00 r
  library setup time                                     -0.02      99.98
  data required time                                                99.98
  --------------------------------------------------------------------------
  data required time                                                99.98
  data arrival time                                                -80.22
  --------------------------------------------------------------------------
  slack (MET)                                                       19.76


  Startpoint: housekeeping/hkspi/wrstb_reg
              (rising edge-triggered flip-flop clocked by hkspi_clk')
  Endpoint: housekeeping/pll_sel_reg[0]
            (rising edge-triggered flip-flop clocked by wbbd_sck_to_csclk_mux)
  Path Group: wbbd_sck_to_csclk_mux
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock hkspi_clk' (rise edge)                          150.00     150.00
  clock network delay (ideal)                             0.00     150.00
  housekeeping/hkspi/wrstb_reg/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00     150.00 r
  housekeeping/hkspi/wrstb_reg/Q (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.02     150.02 r
  housekeeping/hkspi/wrstb (housekeeping_spi)             0.00     150.02 r
  housekeeping/U3607/X (SAEDRVT14_AO21_1)                 0.01     150.04 r
  housekeeping/U1681/X (SAEDRVT14_OAI21_0P75)             0.04     150.07 f
  housekeeping/U1071/X (SAEDRVT14_BUF_S_1)                0.02     150.09 f
  housekeeping/U527/X (SAEDRVT14_INV_1)                   0.01     150.10 r
  housekeeping/U301/X (SAEDRVT14_BUF_S_1)                 0.01     150.12 r
  housekeeping/U311/X (SAEDRVT14_BUF_S_1)                 0.01     150.13 r
  housekeeping/U174/X (SAEDRVT14_ND2_CDC_1)               0.02     150.15 f
  housekeeping/U96/X (SAEDRVT14_INV_1)                    0.01     150.16 r
  housekeeping/U3686/X (SAEDRVT14_OAI22_1)                0.01     150.17 f
  housekeeping/pll_sel_reg[0]/D (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00     150.17 f
  data arrival time                                                150.17

  clock wbbd_sck_to_csclk_mux (rise edge)               160.00     160.00
  clock network delay (ideal)                             0.00     160.00
  housekeeping/pll_sel_reg[0]/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00     160.00 r
  library setup time                                     -0.02     159.98
  data required time                                               159.98
  --------------------------------------------------------------------------
  data required time                                               159.98
  data arrival time                                               -150.17
  --------------------------------------------------------------------------
  slack (MET)                                                        9.81


1


## Question: how to get_pins from all_connected output list?
- use filter to get the MUX output pin connect to housekeeping/csclk

get_pins [all_connected housekeeping/csclk -leaf] -filter "@direction == out"

# final solution
- create_generated_clock & compile 2nd times for patch MUX output pin name(cell name) changed issue
- set_false_path

- sdc file

    set csclk_mux_out_pin [get_pins [all_connected housekeeping/csclk -leaf] -filter "@direction == out"]

    create_generated_clock -name wbbd_sck_to_csclk_mux -source  [get_ports clock] -divide_by 2 $csclk_mux_out_pin 

    create_generated_clock -name hkspi_clk_to_csclk_mux -source [get_ports {mprj_io[4]}] -add -divide_by 1 $csclk_mux_out_pin 

    set_clock_groups -logically_exclusive -name csclk_mux -group wbbd_sck_to_csclk_mux -group hkspi_clk_to_csclk_mux 

- tcl file

source $Constraints_file


set_dont_use [get_lib_cells */*FDN*]

set_fix_multiple_port_nets -outputs -feedthroughs 
source $Warning_file

check_design
link
 
compile -exact_map -map_effort high -area_effort medium -power_effort none

report_clock

create_generated_clock -name wbbd_sck_to_csclk_mux -source  [get_ports clock] -divide_by 2 $csclk_mux_out_pin 

create_generated_clock -name hkspi_clk_to_csclk_mux -source [get_ports {mprj_io[4]}] -add -divide_by 1 $csclk_mux_out_pin 

set_clock_groups -logically_exclusive -name csclk_mux -group wbbd_sck_to_csclk_mux -group hkspi_clk_to_csclk_mux 

set_false_path -from [get_clocks clk] -to [get_clocks hkspi_clk_to_csclk_mux]  
set_false_path -from [get_clocks hkspi_clk] -to [get_clocks wbbd_sck_to_csclk_mux]

report_clock

compile -exact_map -map_effort high -area_effort medium -power_effort none

report_clock

## report_timing result
- hkspi_clk -> hkspi_clk_to_csclk_mux
- clk -> wbbd_sck_to_csclk_mux

report_timing -to [get_pins -of_objects housekeeping/pll_sel_reg[0] -filter "lib_pin_name==D"]
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : caravel_top
Version: U-2022.12
Date   : Thu Feb  1 20:33:59 2024
****************************************

 # A fanout number of 1000 was used for high fanout net computations.

Operating Conditions: tt0p8v25c   Library: saed14rvt_tt0p8v25c
Wire Load Model Mode: top

  Startpoint: housekeeping/hkspi/wrstb_reg
              (rising edge-triggered flip-flop clocked by hkspi_clk')
  Endpoint: housekeeping/pll_sel_reg[0]
            (rising edge-triggered flip-flop clocked by hkspi_clk_to_csclk_mux)
  Path Group: hkspi_clk_to_csclk_mux
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock hkspi_clk' (rise edge)                           50.00      50.00
  clock network delay (ideal)                             0.00      50.00
  housekeeping/hkspi/wrstb_reg/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00      50.00 r
  housekeeping/hkspi/wrstb_reg/Q (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.02      50.02 r
  housekeeping/hkspi/wrstb (housekeeping_spi)             0.00      50.02 r
  housekeeping/U4202/X (SAEDRVT14_INV_1)                  0.00      50.03 f
  housekeeping/U4201/X (SAEDRVT14_OAI22_1)                0.01      50.04 r
  housekeeping/U2296/X (SAEDRVT14_ND2_CDC_1)              0.03      50.07 f
  housekeeping/U1354/X (SAEDRVT14_BUF_S_1)                0.01      50.08 f
  housekeeping/U868/X (SAEDRVT14_BUF_S_1)                 0.01      50.09 f
  housekeeping/U40/X (SAEDRVT14_INV_1)                    0.02      50.10 r
  housekeeping/U343/X (SAEDRVT14_ND2_CDC_1)               0.02      50.12 f
  housekeeping/U127/X (SAEDRVT14_INV_1)                   0.01      50.14 r
  housekeeping/U4329/X (SAEDRVT14_OAI22_1)                0.01      50.15 f
  housekeeping/pll_sel_reg[0]/D (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00      50.15 f
  data arrival time                                                 50.15

  clock hkspi_clk_to_csclk_mux (rise edge)              100.00     100.00
  clock network delay (ideal)                             0.00     100.00
  housekeeping/pll_sel_reg[0]/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00     100.00 r
  library setup time                                     -0.02      99.98
  data required time                                                99.98
  --------------------------------------------------------------------------
  data required time                                                99.98
  data arrival time                                                -50.15
  --------------------------------------------------------------------------
  slack (MET)                                                       49.84


  Startpoint: housekeeping/wbbd_busy_reg
              (rising edge-triggered flip-flop clocked by clk)
  Endpoint: housekeeping/pll_sel_reg[0]
            (rising edge-triggered flip-flop clocked by wbbd_sck_to_csclk_mux)
  Path Group: wbbd_sck_to_csclk_mux
  Path Type: max

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  clock clk (rise edge)                                  20.00      20.00
  clock network delay (ideal)                             0.00      20.00
  housekeeping/wbbd_busy_reg/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00      20.00 r
  housekeeping/wbbd_busy_reg/Q (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.02      20.02 r
  housekeeping/U3676/X (SAEDRVT14_BUF_S_1)                0.01      20.03 r
  housekeeping/U1820/X (SAEDRVT14_INV_1)                  0.01      20.04 f
  housekeeping/U1264/X (SAEDRVT14_BUF_S_1)                0.02      20.06 f
  housekeeping/U1819/X (SAEDRVT14_ND2_CDC_1)              0.01      20.07 r
  housekeeping/U58/X (SAEDRVT14_OAI21_0P75)               0.02      20.08 f
  housekeeping/U1266/X (SAEDRVT14_INV_1)                  0.01      20.10 r
  housekeeping/U718/X (SAEDRVT14_ND2_CDC_1)               0.01      20.11 f
  housekeeping/U1265/X (SAEDRVT14_NR3_1)                  0.02      20.13 r
  housekeeping/U765/X (SAEDRVT14_ND2_CDC_1)               0.01      20.14 f
  housekeeping/U272/X (SAEDRVT14_INV_1)                   0.01      20.15 r
  housekeeping/U343/X (SAEDRVT14_ND2_CDC_1)               0.02      20.17 f
  housekeeping/U127/X (SAEDRVT14_INV_1)                   0.01      20.18 r
  housekeeping/U4329/X (SAEDRVT14_OAI22_1)                0.01      20.19 f
  housekeeping/pll_sel_reg[0]/D (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00      20.19 f
  data arrival time                                                 20.19

  clock wbbd_sck_to_csclk_mux (rise edge)                40.00      40.00
  clock network delay (ideal)                             0.00      40.00
  housekeeping/pll_sel_reg[0]/CK (SAEDRVT14_FDPRBQ_V2_1)
                                                          0.00      40.00 r
  library setup time                                     -0.02      39.98
  data required time                                                39.98
  --------------------------------------------------------------------------
  data required time                                                39.98
  data arrival time                                                -20.19
  --------------------------------------------------------------------------
  slack (MET)                                                       19.79


1

## code reference for housekeeping/pll_sel

module housekeeping (
	...
);

    assign caddr = (wbbd_busy) ? wbbd_addr : iaddr;
    assign csclk = (wbbd_busy) ? wbbd_sck : ((spi_is_active) ? mgmt_gpio_in[4] : 1'b0);
    assign cdata = (wbbd_busy) ? wbbd_data : idata;
    assign cwstb = (wbbd_busy) ? wbbd_write : wrstb;
    ...
    always @(posedge csclk or negedge porb) begin
	if (porb == 1'b0) begin
	
            pll_sel <= 3'b010;		// Default output divider divide-by-2
			
        end else begin
	    if (cwstb == 1'b1) begin
                case (caddr)
            	    ...				
            	    8'h11: begin
                	pll_sel <= cdata[2:0];
            	    end
            	    ...				
        	endcase	// (caddr)
    	    end else begin
	    	serial_xfer <= 1'b0;	// Serial transfer is self-resetting
		irq_spi <= 1'b0;	// IRQ is self-resetting
    	    end
    	end
    end
endmodule	// housekeeping
			

[code link](https://github.com/TonyHo722/caravel-lite/blob/23f2329117ba2744620bd83f7526cb2b876aef67/verilog/rtl/housekeeping.v#L1143)

# final solution

## sdc file
set clk_period 20
create_clock -name clk -period $clk_period [get_ports {clock}]
create_clock -name hkspi_clk -period 100 [get_ports {mprj_io[4]} ]

set wbbd_sck_pin [get_pins -of_objects housekeeping/wbbd_sck -filter lib_pin_name==Q]
create_generated_clock -name wbbd_sck -source [get_ports {housekeeping/wb_clk_i} ] -divide_by 2 $wbbd_sck_pin
create_generated_clock -name wbbd_sck_to_csclk_mux -source [get_ports clock] -divide_by 2 housekeeping/csclk_MUX_dont_touch/X
create_generated_clock -name hkspi_clk_to_csclk_mux -source [get_ports {mprj_io[4]}] -add -divide_by 1 housekeeping/csclk_MUX_dont_touch/X

set_clock_groups \
-name clock_group \
-logically_exclusive \
-group [get_clocks {clk wbbd_sck_to_csclk_mux}]\
-group [get_clocks {ioclk_in rxclk}]\
-group [get_clocks {hk_serial_clk}]\
-group [get_clocks {hk_serial_load}]\
-group [get_clocks {hkspi_clk hkspi_clk_to_csclk_mux}]

## verilog code update

    //assign csclk = (wbbd_busy) ? wbbd_sck : ((spi_is_active) ? mgmt_gpio_in[4] : 1'b0);

    //  create a MUX instance from MUX in EDK lib and set dont_touch then synthesis tool keep this MUX instance for source_object of create_generated_clock in sdc file.
    wire tmp_hkspi_clk;
    assign tmp_hkspi_clk = (spi_is_active) ? mgmt_gpio_in[4] : 1'b0;
    //assign csclk = (wbbd_busy) ? wbbd_sck : tmp_hkspi_clk;
    (* dont_touch = "true" *) SAEDRVT14_MUX2_1_func csclk_MUX_dont_touch(
        .X(csclk),
        .D0(tmp_hkspi_clk),
        .D1(wbbd_sck),
        .S(wbbd_busy)
    );