Caravel reset pin code trace

###### tags: `caraval-fpga-reset` # code trace update in below link [trace code for caravel_user_project mpw-8c](https://hackmd.io/@TonyHo/HyHrruGla) - this document in below is code trace in https://github.com/efabless/caravel and may not sync to mpw-8c. # Caravel reset pin - [Tony] resetb come from testbench when no defined TOP_ROUTING and connect to sky130_fd_io__top_xres4v2 resetb_pad. the resetb_pad output resetb_core_h to caravel.v I suspect in silicon, it should defined TOP_ROUTING, the reset pin is connect to resetb_pad ## trace resetb signal ### gpio_tb.v https://github.com/efabless/caravel/blob/mpw-8c/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v#L78 ``` reg RSTB; ``` https://github.com/efabless/caravel/blob/mpw-8c/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v#L159-L182 ``` caravel uut ( ... .resetb (RSTB) ... ); ``` ### caravel.v https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L61 ``` input resetb, // Reset input (sense inverted) ``` https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L364 ``` chip_io padframe( ... .resetb(resetb), ... ); ``` ### chip_io.v https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/chip_io.v#L56 ``` module chip_io( ... input resetb, ... ); ``` - [Tony] the resetb is only used when no define TOP_ROUTING I think when defined TOP_ROUTING the the reset pin connect to xres_buf and output resetb_core_h - sky130_fd_io__top_xres4v2 - .ENABLE_H(porb_h) for input - .PAD(resetb) for inout - .XRES_H_N(resetb_core_h) for output - reset pin -> resetb, porb_h for enable output, resetb_core_h is output reset signal connect to [rstb_h in caravel.v](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L372) ``` // NOTE: The analog_out pad from the raven chip has been replaced by // the digital reset input resetb on caravel due to the lack of an on-board // power-on-reset circuit. The XRES pad is used for providing a glitch- // free reset. wire xresloop; wire xres_vss_loop; sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING .PAD(resetb), //(inout) `endif .TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h .TIE_HI_ESD(), .TIE_LO_ESD(xres_vss_loop), .PAD_A_ESD_H(xresloop), .XRES_H_N(resetb_core_h), //(output) .DISABLE_PULLUP_H(xres_vss_loop), // 0 = enable pull-up on reset pad .ENABLE_H(porb_h), // Power-on-reset (input) .EN_VDDIO_SIG_H(xres_vss_loop), // No idea. .INP_SEL_H(xres_vss_loop), // 1 = use filt_in_h else filter the pad input .FILT_IN_H(xres_vss_loop), // Alternate input for glitch filter .PULLUP_H(xres_vss_loop), // Pullup connection for alternate filter input .ENABLE_VDDIO(vccd_const_one[6]) ); ``` [code link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/chip_io.v#L299-L323 ) ### module sky130_fd_io__top_xres4v2 https://github.com/efabless/caravel/blob/main/openlane/chip_io/sky130_fd_io__top_xres4v2-stub.v#L1C1-L31C10 ``` module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD, AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H, DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO ,VCCD, VCCHIB, VDDA, VDDIO,VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH ); output XRES_H_N; inout AMUXBUS_A; inout AMUXBUS_B; inout PAD; input DISABLE_PULLUP_H; input ENABLE_H; input EN_VDDIO_SIG_H; input INP_SEL_H; input FILT_IN_H; inout PULLUP_H; input ENABLE_VDDIO; input VCCD; input VCCHIB; input VDDA; input VDDIO; input VDDIO_Q; input VSSA; input VSSD; input VSSIO; input VSSIO_Q; input VSWITCH; inout PAD_A_ESD_H; output TIE_HI_ESD; output TIE_LO_ESD; inout TIE_WEAK_HI_H; endmodule ``` ## trace resetb_core_h signal ### chip_io.v https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/chip_io.v#L64 ``` module chip_io( ... output resetb_core_h, ... ); ``` https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/chip_io.v#L299-L323 ``` sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING .PAD(resetb), `endif ... .XRES_H_N(resetb_core_h), ... ); ``` ### caravel.v ``` module caravel ( ... input resetb, ... ); ... wire rstb_h; chip_io padframe( ... ... .resetb_core_h(rstb_h), //O ... ); ``` [resetb link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L61) [rstb_h link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L372) [Tony] resetb_core_h -> rstb_h -> rstb_l https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L1583-L1593 ``` // XRES (chip input pin reset) reset level converter xres_buf rstb_level ( `ifdef USE_POWER_PINS .VPWR(vddio_core), .LVPWR(vccd_core), .LVGND(vssd_core), .VGND(vssio_core), `endif .A(rstb_h), .X(rstb_l) ); ``` ### Power on reset - por instance in caravel.v ``` simple_por por ( `ifdef USE_POWER_PINS .vdd3v3(vddio_core), .vdd1v8(vccd_core), .vss3v3(vssio_core), .vss1v8(vssd_core), `endif .porb_h(porb_h), //output .porb_l(porb_l), //output .por_l(por_l) //output ); ``` [code link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L1571C1-L1581C7) - module simple_por in simple_por.v ``` module simple_por( `ifdef USE_POWER_PINS inout vdd3v3, inout vdd1v8, inout vss3v3, inout vss1v8, `endif output porb_h, output porb_l, output por_l ); ``` [code link](https://github.com/efabless/caravel/blob/main/verilog/rtl/simple_por.v#L20C1-L30C3) ``` module caravel ( ... ); ... simple_por por ( `ifdef USE_POWER_PINS .vdd3v3(vddio_core), .vdd1v8(vccd_core), .vss3v3(vssio_core), .vss1v8(vssd_core), `endif .porb_h(porb_h), //output .porb_l(porb_l), //output .por_l(por_l) //output ); ... chip_io padframe( ... .porb_h(porb_h), //input .por(por_l_buf), //input ... ); ... mgmt_core_wrapper soc ( ... .por_l_in(por_l), //input .por_l_out(por_l_buf), //output ... ); endmodule ``` [porb_h in padframe code link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L370C1-L371C18) [por_l in soc code link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L500C1-L501C24) ``` ```