# caravel io spec
[caravel io spec](https://hackmd.io/@TonyHo/SJWxQqxqT)

# log files for sdc
[log files](https://drive.google.com/drive/folders/17y7PmdZ6BoEipnxYdS3Tb83Eq875Ahs0?usp=drive_link)

# sdc file study
[sdc file study](https://hackmd.io/@TonyHo/BkkOQ5gq6)

### update sdc for wbbd_sck

create_clock -name clk -period $clk_period [get_ports {clock}]
create_clock -name hkspi_clk -period 100 [get_ports {mprj_io[4]} ]


set wbbd_sck_pin [get_pins -of_objects housekeeping/wbbd_sck -filter lib_pin_name==Q]

create_generated_clock -name "wbbd_sck" -source [get_ports {"housekeeping/wb_clk_i"} ] -divide_by 2 $wbbd_sck_pin

# paths between wb_clk_i and sck shouldn't be timed
set_clock_groups -logically_exclusive -group clk -group hkspi_clk

## dc_shell command : check_timing vs report_timing

check_timing
- Checks for possible timing problems in the current design.

report_timing
- The report_timing command provides detailed, point-by-point timing information for the paths that have the worst slack. You can control the scope of the design that is reported, the number of paths to report, and the types of path information to include in the report. The information in the report can help you determine how to fix the violations.

### issue : Warning: The following end-points are not constrained for maximum delay.

Information: Checking unconstrained_endpoints...

Warning: The following end-points are not constrained for maximum delay.

End point
---------------
gpio
mprj/u_fsic/U_AXIL_AXIS0/axi_ctrl_logic/data_ss_reg[0]/D
...
mprj/u_fsic/U_AXIL_AXIS0/axi_ctrl_logic/data_ss_reg[31]/D
mprj/u_fsic/U_AXIL_AXIS0/axi_ctrl_logic/get_secnd_data_ss_reg/D
mprj/u_fsic/U_AXIL_AXIS0/axi_ctrl_logic/secnd_data_done_reg/D
mprj_io[2]
mprj_io[3]
mprj_io[4]

### not constrained issue in AA
[not constrained issue in AA](https://hackmd.io/@TonyHo/BJmn_sxq6)

## issue : run check_timing in differen timing result is different.
- 是否有些design 被最佳化after synthesis？

always @(posedge sys_clk) begin

    multiregimpl3_regs0 <= la_input[0];
    multiregimpl3_regs1 <= multiregimpl3_regs0;

- 0125_fix_clock_issue_2\timing_caravel_top_check_timing.log

Information: Checking unconstrained_endpoints...

Warning: The following end-points are not constrained for maximum delay.

End point
---------------
soc/core/multiregimpl3_regs0_reg/next_state

- 0125_fix_clock_issue_2\timing_caravel_top_check_timing_end.log
No Warning

- get level net list found multiregimpl3_regs0_reg

  SAEDRVT14_FDP_V2_1 multiregimpl3_regs0_reg ( .D(la_input[0]), .CK(core_clk), 
        .Q(multiregimpl3_regs0) );

### remove set_propagated_clock in sdc file for synthsis

## issue - Error: 'set_input_transition' cannot be set on an output port 'flash_io1'. (UID-91)

source $Constraints_file
[INFO]: IO[4] is set as: SCK
[INFO]: GPIOs mode is set as: OUT
[INFO]: System clock period: 100
Warning: It is dangerous to create a clock source on inout port 'mprj_io[36]'. (UID-376)
[INFO]: io clock period: 25
Information: set_input_delay values are added to the propagated clock skew. (TIM-113)
[INFO]: Clock transition range: 1 : 1.5
Warning: It is dangerous to create a clock source on inout port 'mprj_io[4]'. (UID-376)
Information: set_input_delay values are added to the propagated clock skew. (TIM-113)
[INFO]: Setting input delay to: 4
[INFO]: Setting output delay to: 4
[INFO]: Input transition range: 1 : 4
[INFO]: Cap load range: 4 : 7
[INFO]: Flash interface transition range: 4 : 6
Error: 'set_input_transition' cannot be set on an output port 'flash_io1'. (UID-91)
Error: 'set_input_transition' cannot be set on an output port 'flash_io1'. (UID-91)
[INFO]: Flash interface cap load range: 6 : 8
[INFO]: Flash interface delay: input 4 output 4
Error: Invalid delay direction for port 'flash_io1'. (UID-254)
Current design is 'caravel_top'.
[INFO]: Setting derate factor to: 3.75 %
1
set_dont_use [get_lib_cells */*FDN*]
1
set_fix_multiple_port_nets -outputs -feedthroughs 
1

- Question: Why caravel set flash_io1 is output in verilog code and no sync to sdc file?

    output flash_io0,
    output flash_io1

[code link](https://github.com/TonyHo722/caravel-lite/blob/fsic/verilog/rtl/caravel.v#L70C1-L71C21)

- sdc file

set_input_transition -min $flash_min_tran [get_ports {flash_io1}]
set_input_transition -max $flash_max_tran [get_ports {flash_io1}]

- update carave_top.v as input for flash_io1 to fixed this issue

- system behavior.

flash_io0 is output
flash_io1 is input

## Timing loop detected

Information: Timing loop detected. (OPT-150)
	clock_ctrl/divider/syncN_reg[1]/CK clock_ctrl/divider/syncN_reg[1]/Q clock_ctrl/divider/U8/A1 clock_ctrl/divider/U8/X clock_ctrl/divider/even_0/U3/A1 clock_ctrl/divider/even_0/U3/X clock_ctrl/divider/U5/A1 clock_ctrl/divider/U5/X 
Information: Timing loop detected. (OPT-150)
	clock_ctrl/divider/syncN_reg[2]/CK clock_ctrl/divider/syncN_reg[2]/Q clock_ctrl/divider/U8/A2 clock_ctrl/divider/U8/X clock_ctrl/divider/even_0/U3/A1 clock_ctrl/divider/even_0/U3/X clock_ctrl/divider/U5/A1 clock_ctrl/divider/U5/X 
Warning: Disabling timing arc between pins 'CK' and 'Q' on cell 'clock_ctrl/divider/syncN_reg[1]'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'CK' and 'Q' on cell 'clock_ctrl/divider/syncN_reg[2]'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'CK' and 'Q' on cell 'clock_ctrl/divider/syncN_reg[0]'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'R_EN' and 'DOUT' on cell 'padframe/mprj_pads/area1_io_pad[4]/gpiov2_pad'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'A3' and 'X' on cell 'housekeeping/U3682'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'A3' and 'X' on cell 'housekeeping/U3682'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'A3' and 'X' on cell 'housekeeping/U3682'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'A3' and 'X' on cell 'housekeeping/U3682'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'CK' and 'Q' on cell 'clock_ctrl/divider2/syncN_reg[1]'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'CK' and 'Q' on cell 'clock_ctrl/divider2/syncN_reg[2]'
         to break a timing loop. (OPT-314)
Warning: Disabling timing arc between pins 'CK' and 'Q' on cell 'clock_ctrl/divider2/syncN_reg[0]'
         to break a timing loop. (OPT-314)


## Question: no clock issue
- csclk

    assign csclk = (wbbd_busy) ? wbbd_sck : ((spi_is_active) ? mgmt_gpio_in[4] : 1'b0);

[code link](https://github.com/TonyHo722/caravel-lite/blob/23f2329117ba2744620bd83f7526cb2b876aef67/verilog/rtl/housekeeping.v#L1037C1-L1037C88)

### add create_generated_clock for csclk
[add create_generated_clock for csclk](https://hackmd.io/@TonyHo/SyS7UqN56)

### refernce
[housekeeping clock "csclk" isn't synthesised as a clock #115](https://github.com/efabless/caravel/issues/115)

[housekeeping.sdc](https://github.com/kareefardi/caravel/blob/openlane_config_updates/sdc/housekeeping.sdc)

# Question: does clk buffer add by cts?
- I can't find clk buffer in gl file.

## issue: timing_requirements -ignored

****************************************
Report : timing_requirements
        -ignored
Design : caravel_top
Version: U-2022.12
Date   : Wed Jan 24 10:04:27 2024
****************************************

Description                            Setup               Hold
--------------------------------------------------------------------------------
INVALID TO OBJECT                      FALSE               FALSE
    -to      mprj_io[36]

# message

source $Constraints_file
[INFO]: IO[4] is set as: SCK
[INFO]: GPIOs mode is set as: OUT
[INFO]: System clock period: 20
Warning: It is dangerous to create a clock source on inout port 'mprj_io[36]'. (UID-376)
[INFO]: io clock period: 5
Information: set_input_delay values are added to the propagated clock skew. (TIM-113)
[INFO]: Clock transition range: 1 : 1.5
Warning: It is dangerous to create a clock source on inout port 'mprj_io[4]'. (UID-376)
Information: set_input_delay values are added to the propagated clock skew. (TIM-113)
[INFO]: Setting input delay to: 4
[INFO]: Setting output delay to: 4
[INFO]: Input transition range: 1 : 4
[INFO]: Cap load range: 4 : 7
[INFO]: Flash interface transition range: 4 : 6
[INFO]: Flash interface cap load range: 6 : 8
[INFO]: Flash interface delay: input 4 output 4
Current design is 'caravel_top'.
[INFO]: Setting derate factor to: 3.75 %

# Question list
- [Question: does it need to replace hk_serial_clk from create_clock to create_generated_clock](https://hackmd.io/@TonyHo/SJ78wfaY6)
- [Question in Mux](https://hackmd.io/@TonyHo/BkkOQ5gq6)
- Question: does clk buffer add by cts?