0922 status - AA irq issue and hold time issue

[fail log commit](https://github.com/TonyHo722/caravel-lab/commit/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4) - found this issue after after add AA code [fail log run_fsic.log](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log) # error log - hold violation [hold violation fail log in run_fsic.log](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log#L1102) - port ``irq'' is not a port of mprj [irq issue fail log in run_fsic.log](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log#L2394) ``` tonyho@HLS05:~/workspace/fsic/caravel-lab/bash_auto/hls05$ grep -n -i 'error' run_fsic.log 1102:[ERROR]: There are hold violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.min.rpt'. 1108:[ERROR]: Flow failed. 1115:make[1]: *** [Makefile:73: user_proj_example] Error 255 1119:make: *** [Makefile:107: user_proj_example] Error 2 2044:[ERROR]: There are violations in the design after detailed routing. 2045:[ERROR]: Total Number of violations is 1 2051:[ERROR]: Flow failed. 2053:make[1]: *** [Makefile:73: user_project_wrapper] Error 255 2057:make: *** [Makefile:107: user_project_wrapper] Error 2 2394:/home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/verilog/gl/user_project_wrapper.v:57: error: port ``irq'' is not a port of mprj. 2396:1 error(s) during elaboration. 2401:make: *** [system_test111.vvp] Error 1 2403:make: *** [Makefile:153: verify-system_test111-gl] Error 2 5782:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 5867:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 6027:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 9442:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 9795:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 10025:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 11091:Warning: /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/caravel/signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef line 9225, syntax error, unexpected CAP, expecting KW_P or KW_I. 13359:Warning: /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/caravel/signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef line 9225, syntax error, unexpected CAP, expecting KW_P or KW_I. 15627:Warning: /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/caravel/signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef line 9225, syntax error, unexpected CAP, expecting KW_P or KW_I. ``` # hold violations ``` [INFO]: Created manufacturability report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/metrics.csv'. [WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [ERROR]: There are hold violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.min.rpt'. ``` [error log link](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log#L1102) ## [1st error in 26-rcx_sta.min.rpt](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/log/0922_error_log/26-rcx_sta.min.rpt#L386C1-L458C58) ``` Startpoint: _8639_ (rising edge-triggered flip-flop clocked by wb_clk_i) Endpoint: _7775_ (rising edge-triggered flip-flop clocked by wb_clk_i) Path Group: wb_clk_i Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock wb_clk_i (rise edge) 0.00 0.00 clock source latency 0.31 0.20 0.20 ^ wb_clk_i (in) 2 0.07 wb_clk_i (net) 0.31 0.00 0.20 ^ clkbuf_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.11 0.25 0.45 ^ clkbuf_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 4 0.09 clknet_0_wb_clk_i (net) 0.11 0.00 0.45 ^ clkbuf_1_1_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.13 0.58 ^ clkbuf_1_1_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_1_0_wb_clk_i (net) 0.03 0.00 0.59 ^ clkbuf_1_1_1_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.13 0.18 0.76 ^ clkbuf_1_1_1_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.07 clknet_1_1_1_wb_clk_i (net) 0.13 0.00 0.76 ^ clkbuf_2_2_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.14 0.22 0.98 ^ clkbuf_2_2_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.08 clknet_2_2_0_wb_clk_i (net) 0.14 0.00 0.99 ^ clkbuf_3_4_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.48 0.45 1.43 ^ clkbuf_3_4_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 26 0.29 clknet_3_4_0_wb_clk_i (net) 0.48 0.02 1.45 ^ clkbuf_leaf_73_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.08 0.25 1.70 ^ clkbuf_leaf_73_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 17 0.05 clknet_leaf_73_wb_clk_i (net) 0.08 0.00 1.70 ^ _8639_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.10 0.35 2.06 ^ _8639_/Q (sky130_fd_sc_hd__dfrtp_1) 2 0.01 u_fsic.U_CFG_CTRL0.axi_wdata_o[31] (net) 0.10 0.00 2.06 ^ _5072_/A1 (sky130_fd_sc_hd__mux2_1) 0.04 0.13 2.19 ^ _5072_/X (sky130_fd_sc_hd__mux2_1) 1 0.00 _2258_ (net) 0.04 0.00 2.19 ^ _5073_/A (sky130_fd_sc_hd__clkbuf_1) 0.04 0.07 2.26 ^ _5073_/X (sky130_fd_sc_hd__clkbuf_1) 1 0.00 _0406_ (net) 0.04 0.00 2.26 ^ _7775_/D (sky130_fd_sc_hd__dfrtp_1) 2.26 data arrival time 0.00 0.00 clock wb_clk_i (rise edge) 0.00 0.00 clock source latency 0.31 0.23 0.23 ^ wb_clk_i (in) 2 0.07 wb_clk_i (net) 0.31 0.00 0.23 ^ clkbuf_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.11 0.27 0.50 ^ clkbuf_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 4 0.09 clknet_0_wb_clk_i (net) 0.11 0.00 0.50 ^ clkbuf_1_0_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.15 0.65 ^ clkbuf_1_0_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_0_0_wb_clk_i (net) 0.03 0.00 0.65 ^ clkbuf_1_0_1_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.23 0.27 0.92 ^ clkbuf_1_0_1_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.13 clknet_1_0_1_wb_clk_i (net) 0.23 0.00 0.93 ^ clkbuf_2_0_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.24 0.34 1.27 ^ clkbuf_2_0_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.14 clknet_2_0_0_wb_clk_i (net) 0.24 0.01 1.27 ^ clkbuf_3_1_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.55 0.57 1.84 ^ clkbuf_3_1_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 26 0.32 clknet_3_1_0_wb_clk_i (net) 0.55 0.02 1.86 ^ clkbuf_leaf_79_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.08 0.29 2.15 ^ clkbuf_leaf_79_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 14 0.05 clknet_leaf_79_wb_clk_i (net) 0.08 0.00 2.15 ^ _7775_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.25 2.40 clock uncertainty -0.05 2.35 clock reconvergence pessimism -0.03 2.32 library hold time 2.32 data required time ----------------------------------------------------------------------------- 2.32 data required time -2.26 data arrival time ----------------------------------------------------------------------------- -0.06 slack (VIOLATED) ``` ## [2nd error in 26-rcx_sta.min.rpt](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/log/0922_error_log/26-rcx_sta.min.rpt#L461C1-L533C58) - check sky130_fd_sc_hd__dfrtp_1 ``` Startpoint: _8436_ (rising edge-triggered flip-flop clocked by wb_clk_i) Endpoint: _7711_ (rising edge-triggered flip-flop clocked by wb_clk_i) Path Group: wb_clk_i Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock wb_clk_i (rise edge) 0.00 0.00 clock source latency 0.31 0.20 0.20 ^ wb_clk_i (in) 2 0.07 wb_clk_i (net) 0.31 0.00 0.20 ^ clkbuf_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.11 0.25 0.45 ^ clkbuf_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 4 0.09 clknet_0_wb_clk_i (net) 0.11 0.00 0.45 ^ clkbuf_1_1_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.13 0.58 ^ clkbuf_1_1_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_1_0_wb_clk_i (net) 0.03 0.00 0.59 ^ clkbuf_1_1_1_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.13 0.18 0.76 ^ clkbuf_1_1_1_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.07 clknet_1_1_1_wb_clk_i (net) 0.13 0.00 0.76 ^ clkbuf_2_2_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.14 0.22 0.98 ^ clkbuf_2_2_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.08 clknet_2_2_0_wb_clk_i (net) 0.14 0.00 0.99 ^ clkbuf_3_4_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.48 0.45 1.43 ^ clkbuf_3_4_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 26 0.29 clknet_3_4_0_wb_clk_i (net) 0.48 0.01 1.44 ^ clkbuf_leaf_76_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.08 0.25 1.69 ^ clkbuf_leaf_76_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 15 0.05 clknet_leaf_76_wb_clk_i (net) 0.08 0.00 1.69 ^ _8436_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.15 0.39 2.08 ^ _8436_/Q (sky130_fd_sc_hd__dfrtp_1) 2 0.02 u_fsic.U_AXIL_AXIS0.axi_ctrl_logic.bk_ls_rdata[1] (net) 0.15 0.00 2.08 ^ _4937_/A1 (sky130_fd_sc_hd__mux2_1) 0.04 0.14 2.23 ^ _4937_/X (sky130_fd_sc_hd__mux2_1) 1 0.00 _2187_ (net) 0.04 0.00 2.23 ^ _4938_/A (sky130_fd_sc_hd__clkbuf_1) 0.04 0.07 2.30 ^ _4938_/X (sky130_fd_sc_hd__clkbuf_1) 1 0.00 _0342_ (net) 0.04 0.00 2.30 ^ _7711_/D (sky130_fd_sc_hd__dfrtp_1) 2.30 data arrival time 0.00 0.00 clock wb_clk_i (rise edge) 0.00 0.00 clock source latency 0.31 0.23 0.23 ^ wb_clk_i (in) 2 0.07 wb_clk_i (net) 0.31 0.00 0.23 ^ clkbuf_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.11 0.27 0.50 ^ clkbuf_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 4 0.09 clknet_0_wb_clk_i (net) 0.11 0.00 0.50 ^ clkbuf_1_0_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.15 0.65 ^ clkbuf_1_0_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_0_0_wb_clk_i (net) 0.03 0.00 0.65 ^ clkbuf_1_0_1_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.23 0.27 0.92 ^ clkbuf_1_0_1_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.13 clknet_1_0_1_wb_clk_i (net) 0.23 0.00 0.93 ^ clkbuf_2_0_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.24 0.34 1.27 ^ clkbuf_2_0_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.14 clknet_2_0_0_wb_clk_i (net) 0.24 0.01 1.27 ^ clkbuf_3_1_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.55 0.57 1.84 ^ clkbuf_3_1_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 26 0.32 clknet_3_1_0_wb_clk_i (net) 0.55 0.02 1.86 ^ clkbuf_leaf_82_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.09 0.30 2.16 ^ clkbuf_leaf_82_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 18 0.06 clknet_leaf_82_wb_clk_i (net) 0.09 0.00 2.16 ^ _7711_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.25 2.41 clock uncertainty -0.05 2.36 clock reconvergence pessimism -0.03 2.33 library hold time 2.33 data required time ----------------------------------------------------------------------------- 2.33 data required time -2.30 data arrival time ----------------------------------------------------------------------------- -0.04 slack (VIOLATED) ``` ## [3rd error in 26-rcx_sta.min.rpt](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/log/0922_error_log/26-rcx_sta.min.rpt#L536C1-L608C58) ``` Startpoint: _8637_ (rising edge-triggered flip-flop clocked by wb_clk_i) Endpoint: _7773_ (rising edge-triggered flip-flop clocked by wb_clk_i) Path Group: wb_clk_i Path Type: min Fanout Cap Slew Delay Time Description ----------------------------------------------------------------------------- 0.00 0.00 clock wb_clk_i (rise edge) 0.00 0.00 clock source latency 0.31 0.20 0.20 ^ wb_clk_i (in) 2 0.07 wb_clk_i (net) 0.31 0.00 0.20 ^ clkbuf_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.11 0.25 0.45 ^ clkbuf_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 4 0.09 clknet_0_wb_clk_i (net) 0.11 0.00 0.45 ^ clkbuf_1_1_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.13 0.58 ^ clkbuf_1_1_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_1_0_wb_clk_i (net) 0.03 0.00 0.59 ^ clkbuf_1_1_1_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.13 0.18 0.76 ^ clkbuf_1_1_1_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.07 clknet_1_1_1_wb_clk_i (net) 0.13 0.00 0.76 ^ clkbuf_2_2_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.14 0.22 0.98 ^ clkbuf_2_2_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.08 clknet_2_2_0_wb_clk_i (net) 0.14 0.00 0.99 ^ clkbuf_3_4_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.48 0.45 1.43 ^ clkbuf_3_4_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 26 0.29 clknet_3_4_0_wb_clk_i (net) 0.48 0.02 1.45 ^ clkbuf_leaf_73_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.08 0.25 1.70 ^ clkbuf_leaf_73_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 17 0.05 clknet_leaf_73_wb_clk_i (net) 0.08 0.00 1.70 ^ _8637_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.11 0.36 2.07 ^ _8637_/Q (sky130_fd_sc_hd__dfrtp_1) 2 0.01 u_fsic.U_CFG_CTRL0.axi_wdata_o[29] (net) 0.11 0.00 2.07 ^ _5068_/A1 (sky130_fd_sc_hd__mux2_1) 0.06 0.15 2.21 ^ _5068_/X (sky130_fd_sc_hd__mux2_1) 1 0.00 _2256_ (net) 0.06 0.00 2.21 ^ _5069_/A (sky130_fd_sc_hd__clkbuf_1) 0.05 0.08 2.30 ^ _5069_/X (sky130_fd_sc_hd__clkbuf_1) 1 0.00 _0404_ (net) 0.05 0.00 2.30 ^ _7773_/D (sky130_fd_sc_hd__dfrtp_1) 2.30 data arrival time 0.00 0.00 clock wb_clk_i (rise edge) 0.00 0.00 clock source latency 0.31 0.23 0.23 ^ wb_clk_i (in) 2 0.07 wb_clk_i (net) 0.31 0.00 0.23 ^ clkbuf_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.11 0.27 0.50 ^ clkbuf_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 4 0.09 clknet_0_wb_clk_i (net) 0.11 0.00 0.50 ^ clkbuf_1_0_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.03 0.15 0.65 ^ clkbuf_1_0_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 1 0.01 clknet_1_0_0_wb_clk_i (net) 0.03 0.00 0.65 ^ clkbuf_1_0_1_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.23 0.27 0.92 ^ clkbuf_1_0_1_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.13 clknet_1_0_1_wb_clk_i (net) 0.23 0.00 0.93 ^ clkbuf_2_0_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.24 0.34 1.27 ^ clkbuf_2_0_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 4 0.14 clknet_2_0_0_wb_clk_i (net) 0.24 0.01 1.27 ^ clkbuf_3_1_0_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_8) 0.55 0.57 1.84 ^ clkbuf_3_1_0_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_8) 26 0.32 clknet_3_1_0_wb_clk_i (net) 0.55 0.02 1.86 ^ clkbuf_leaf_82_wb_clk_i/A (sky130_fd_sc_hd__clkbuf_16) 0.09 0.30 2.16 ^ clkbuf_leaf_82_wb_clk_i/X (sky130_fd_sc_hd__clkbuf_16) 18 0.06 clknet_leaf_82_wb_clk_i (net) 0.09 0.00 2.16 ^ _7773_/CLK (sky130_fd_sc_hd__dfrtp_1) 0.25 2.41 clock uncertainty -0.05 2.36 clock reconvergence pessimism -0.03 2.33 library hold time 2.33 data required time ----------------------------------------------------------------------------- 2.33 data required time -2.30 data arrival time ----------------------------------------------------------------------------- -0.03 slack (VIOLATED) ``` ## [irq issue in verilog/gl/user_project_wrapper.v](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/log/0922_error_log/user_project_wrapper.v) - compare gcd and fsic in user_project_wrapper.v ![](https://hackmd.io/_uploads/S1v4Pnq1a.png) - compare gcd and fsic in user_proj_example.v ![](https://hackmd.io/_uploads/ryyOPnq1T.png) ## error check in log file ``` tonyho@HLS05:~/workspace/fsic/caravel-lab/bash_auto/hls05$ grep -n -i 'error' run_fsic.log 1102:[ERROR]: There are hold violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.min.rpt'. 1108:[ERROR]: Flow failed. 1115:make[1]: *** [Makefile:73: user_proj_example] Error 255 1119:make: *** [Makefile:107: user_proj_example] Error 2 2044:[ERROR]: There are violations in the design after detailed routing. 2045:[ERROR]: Total Number of violations is 1 2051:[ERROR]: Flow failed. 2053:make[1]: *** [Makefile:73: user_project_wrapper] Error 255 2057:make: *** [Makefile:107: user_project_wrapper] Error 2 2394:/home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/verilog/gl/user_project_wrapper.v:57: error: port ``irq'' is not a port of mprj. 2396:1 error(s) during elaboration. 2401:make: *** [system_test111.vvp] Error 1 2403:make: *** [Makefile:153: verify-system_test111-gl] Error 2 5782:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 5867:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 6027:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 9442:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 9795:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 10025:[WARNING ODB-0229] Error: library (sky130_sram_2kbyte_1rw1r_32x512_8) already exists 11091:Warning: /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/caravel/signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef line 9225, syntax error, unexpected CAP, expecting KW_P or KW_I. 13359:Warning: /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/caravel/signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef line 9225, syntax error, unexpected CAP, expecting KW_P or KW_I. 15627:Warning: /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/caravel/signoff/chip_io/openlane-signoff/spef/chip_io.nom.spef line 9225, syntax error, unexpected CAP, expecting KW_P or KW_I. ``` - user_proj_example error ``` [STEP 36] [INFO]: Running OpenROAD Antenna Rule Checker (log: ../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/logs/signoff/36-antenna.log)... [INFO]: Saving current set of views in '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/results/final'... [INFO]: Saving current set of views in '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project'... [INFO]: Saving runtime environment... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/metrics.csv'. [WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [ERROR]: There are hold violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.min.rpt'. [INFO]: Saving current set of views in '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/results/final'... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/metrics.csv'. [INFO]: Saving runtime environment... [ERROR]: Flow failed. [INFO]: The failure may have been because of the following warnings: [WARNING]: There are max slew violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max fanout violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. [WARNING]: There are max capacitance violations in the design at the typical corner. Please refer to '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_proj_example/runs/23_09_21_22_17/reports/signoff/26-rcx_sta.slew.rpt'. Reaping losing child 0x55cd4b498410 PID 2075650 make[1]: *** [Makefile:73: user_proj_example] Error 255 ``` [user_proj_example error link](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log#L1091C1-L1115C56) - user_project_wrapper error - the gl files is created after step 30. in this case it stop in step 13 then no gl files be created. ``` [STEP 13] [INFO]: Running Detailed Routing (log: ../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_project_wrapper/runs/23_09_21_22_28/logs/routing/13-detailed.log)... [ERROR]: There are violations in the design after detailed routing. [ERROR]: Total Number of violations is 1 [INFO]: Saving current set of views in '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_project_wrapper/runs/23_09_21_22_28/results/final'... [INFO]: Generating final set of reports... [INFO]: Created manufacturability report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_project_wrapper/runs/23_09_21_22_28/reports/manufacturability.rpt'. [INFO]: Created metrics report at '../home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/openlane/user_project_wrapper/runs/23_09_21_22_28/reports/metrics.csv'. [INFO]: Saving runtime environment... [ERROR]: Flow failed. Reaping losing child 0x55f57bc47430 PID 2077225 make[1]: *** [Makefile:73: user_project_wrapper] Error 255 ``` [user_project_wrapper error link](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log#[L2044](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log#L2042C1-L2053C59)) - verify-system_test111-gl error - the gl/user_project_wrapper.v is a old file in the folder, it is not created from current rtl/user_project_wrapper.v then cause this issue - if I remove gl/user_project_wrapper.v before running make verify-system_test111-gl then it will report not found gl/user_project_wrapper.v ``` Must remake target `system_test111.vvp'. Invoking recipe from /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/mgmt_core_wrapper/verilog/dv/make/sim.makefile:82 to update target `system_test111.vvp'. iverilog -Ttyp -DFUNCTIONAL -DGL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \ -g2012 \ -f/home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/mgmt_core_wrapper/verilog/includes/includes.gl.caravel \ -f/home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/verilog/includes/includes.gl.caravel_user_project -o system_test111.vvp system_test111_tb.v Putting child 0x2477780 (system_test111.vvp) PID 33 on the chain. Live child 0x2477780 (system_test111.vvp) PID 33 /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/verilog/gl/user_project_wrapper.v:57: error: port ``irq'' is not a port of mprj. /home/tonyho/workspace/debug/fsic_0921_AA/caravel_user_project/caravel/verilog/gl/caravel.v:4988: warning: input port clock is coerced to inout. ``` [verify-system_test111-gl error link](https://github.com/TonyHo722/caravel-lab/blob/7a355cfcd62f65fd3277323ce4a572b5d5ae51f4/bash_auto/hls05/run_fsic.log#L2386C1-L2395C145) ### use branch: [0923_AA_irq_issue](https://github.com/TonyHo722/caravel-lab/tree/0923_AA_irq_issue) to check this issue [TODO] - in ubuntu5 - I remove gl file before make user_proj_example - I expect the gl file should be created by - make user_proj_example - make user_project_wrapper - due to AA module casue hold violate ### check AA irq issue in hls05 by remove gl file [TODO] - branch: 0923_AA_irq_issue_hls05_repo ### remove gl file in gcd in hls05 [TODO] - branch: 0923_AA_irq_issue_hls05_repo