trace code for caravel_user_project mpw-8c

# github - main repo in tag=mpw-8c https://github.com/efabless/caravel_user_project/tree/mpw-8c - sub-module in tag=mpw-8c https://github.com/efabless/caravel-lite/tree/mpw-8c https://github.com/efabless/caravel_mgmt_soc_litex/tree/mpw-8c ## caravel.v https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v ## caravan.v https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravan.v ## mgmt_core_wrapper.v https://github.com/efabless/caravel_mgmt_soc_litex/blob/mpw-8c/verilog/rtl/mgmt_core_wrapper.v # Power on Reset(POR) in caravel.v ## 1. trace code : (por_l) -> (por_l_buf) - detail code trace in below - simple_por output por_l, mgmt_core_wrapper transfer it to por_l_buf - [simple_por] -> por_l => (por_l) => por_l_in -> [mgmt_core_wrapper] -> por_l_out => (por_l_buf) ``` module caravel ( ... ); mgmt_core_wrapper soc ( ... .por_l_in(por_l), //input .por_l_out(por_l_buf), //ouput ... ); simple_por por ( ... .porb_h(porb_h), //output .porb_l(porb_l), //output .por_l(por_l) //output ); ... endmodule ``` [por_l in mgmt_core_wrapper](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L500C1-L501C24) [porb_h in simple_por](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L1571C1-L1581C7) ### module simple_por ``` module simple_por( `ifdef USE_POWER_PINS inout vdd3v3, inout vdd1v8, inout vss3v3, inout vss1v8, `endif output porb_h, output porb_l, output por_l ); ``` [code link](https://github.com/efabless/caravel-lite/blob/main/verilog/rtl/simple_por.v#L20C1-L30C3) ### module mgmt_core_wrapper ``` module mgmt_core_wrapper ( ... input por_l_in, ... output por_l_out, ... ); mgmt_core core ( ... .por_l_in(por_l_in), .por_l_out(por_l_out), ... ); ... endmodule ``` [por_l_in in mgmt_core_wrapper](https://github.com/efabless/caravel_mgmt_soc_litex/blob/mpw-8c/verilog/rtl/mgmt_core_wrapper.v#L58C20-L58C20) [por_l_in in mgmt_core](https://github.com/efabless/caravel_mgmt_soc_litex/blob/mpw-8c/verilog/rtl/mgmt_core_wrapper.v#L175C1-L176C31) #### module mgmt_core ``` module mgmt_core( ... input wire por_l_in, output wire por_l_out, ); ... assign por_l_out = por_l_in; ... endmodule ``` [code link](https://github.com/efabless/caravel_mgmt_soc_litex/blob/main/verilog/rtl/mgmt_core.v#L79C1-L80C24) ## 2. trace code : (por_l_buf) Why chip_io need (por_h) and (por_l_buf) ? - (por_l_buf) -> por -> [chip_io] - [Answer] por is no used in chip_io ``` module caravel ( ... ); chip_io padframe( ... .porb_h(porb_h), //input .por(por_l_buf), //input (no used in chip_io) ... ); mgmt_core_wrapper soc ( ... .por_l_in(por_l), //input .por_l_out(por_l_buf), //ouput ... ); simple_por por ( ... .porb_h(porb_h), //output .porb_l(porb_l), //output .por_l(por_l) //output ); ... endmodule ``` [porb_h in chip_io](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L370C1-L370C18) ## 3. trace code : (porb_h) - (porb_h) connect to below modules - sky130_fd_io__top_xres4v2 - sky130_ef_io__gpiov2_pad_wrapped ## module chip_io use porb_h ``` module chip_io( ... input porb_h, input por, //input (no used in chip_io) ... ); ... sky130_fd_io__top_xres4v2 resetb_pad ( ... .ENABLE_H(porb_h), // Power-on-reset ... ); ... mprj_io mprj_pads( ... .porb_h(porb_h), ... ); ... endmodule ``` [porb_h in chip_io](https://github.com/efabless/caravel-lite/blob/main/verilog/rtl/chip_io.v#L62C2-L63C13) [porb_h in sky130_fd_io__top_xres4v2](https://github.com/efabless/caravel-lite/blob/main/verilog/rtl/chip_io.v#L317C3-L317C23) [porb_h in mprj_io](https://github.com/efabless/caravel-lite/blob/main/verilog/rtl/chip_io.v#L390C3-L390C19) ## module mprj_io use porb_h ``` module mprj_io ( ... input porb_h, ... ); ... sky130_ef_io__gpiov2_pad_wrapped area1_io_pad [AREA1PADS - 1:0] ( ... .ENABLE_VDDA_H(porb_h), ... ); ... sky130_ef_io__gpiov2_pad_wrapped area2_io_pad [TOTAL_PADS - AREA1PADS - 1:0] ( ... .ENABLE_VDDA_H(porb_h), ... ); ... endmodule ``` [code link](https://github.com/efabless/caravel-lite/blob/main/verilog/rtl/mprj_io.v#L82) # trace resetb signal from testbeench ## gpio_tb.v - RSTB -> resetb ``` reg RSTB; ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v#L78) ``` caravel uut ( ... .resetb (RSTB) ... ); ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/dv/caravel/mgmt_soc/gpio/gpio_tb.v#L181) ## caravel.v - RSTB -> resetb -> rstb_h ``` module caravel ( ... input resetb, // Reset input (sense inverted) ... ); ... endmodule ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L61) ``` chip_io padframe( ... .resetb(resetb), //input ... .resetb_core_h(rstb_h), //output ... ); ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L364) ## chip_io.v - RSTB -> resetb -> [resetb -> resetb_core_h] -> rstb_h ``` module chip_io( ... input resetb, ... output resetb_core_h, ); ... sky130_fd_io__top_xres4v2 resetb_pad ( .PAD(resetb), //(inout) ... .XRES_H_N(resetb_core_h), //(output) ... .ENABLE_H(porb_h), // Power-on-reset (input) ... ); endmodule ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/chip_io.v#L56) - sky130_fd_io__top_xres4v2 - .ENABLE_H(porb_h) for input - .PAD(resetb) for inout - .XRES_H_N(resetb_core_h) for output - reset pin -> resetb, porb_h for enable output, resetb_core_h is output reset signal connect to [rstb_h in caravel.v](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L372) ``` ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/chip_io.v#L306C2-L323C8) ### module sky130_fd_io__top_xres4v2 https://github.com/efabless/caravel/blob/main/openlane/chip_io/sky130_fd_io__top_xres4v2-stub.v#L1C1-L31C10 ``` module sky130_fd_io__top_xres4v2 ( TIE_WEAK_HI_H, XRES_H_N, TIE_HI_ESD, TIE_LO_ESD, AMUXBUS_A, AMUXBUS_B, PAD, PAD_A_ESD_H, ENABLE_H, EN_VDDIO_SIG_H, INP_SEL_H, FILT_IN_H, DISABLE_PULLUP_H, PULLUP_H, ENABLE_VDDIO ,VCCD, VCCHIB, VDDA, VDDIO,VDDIO_Q, VSSA, VSSD, VSSIO, VSSIO_Q, VSWITCH ); output XRES_H_N; inout AMUXBUS_A; inout AMUXBUS_B; inout PAD; input DISABLE_PULLUP_H; input ENABLE_H; input EN_VDDIO_SIG_H; input INP_SEL_H; input FILT_IN_H; inout PULLUP_H; input ENABLE_VDDIO; input VCCD; input VCCHIB; input VDDA; input VDDIO; input VDDIO_Q; input VSSA; input VSSD; input VSSIO; input VSSIO_Q; input VSWITCH; inout PAD_A_ESD_H; output TIE_HI_ESD; output TIE_LO_ESD; inout TIE_WEAK_HI_H; endmodule ``` ## caravel.v - RSTB -> resetb -> rstb_h -> rstb_l ``` xres_buf rstb_level ( ... .A(rstb_h), //input .X(rstb_l) //ouput ); ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L1591) ## caravel.v - RSTB -> resetb -> rstb_h -> rstb_l -> rstb_l_buf ``` mgmt_core_wrapper soc ( ... .rstb_l_in(rstb_l), .rstb_l_out(rstb_l_buf), ... ); ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L497) ### mgmt_core_wrapper.v - RSTB -> resetb -> rstb_h -> rstb_l -> [rstb_l_in -> rstb_l_out] -> rstb_l_buf ``` module mgmt_core_wrapper ( ... input rstb_l_in, ... output rstb_l_out, ... ); ... mgmt_core core ( ... .rstb_l_in(rstb_l_in), .rstb_l_out(rstb_l_out), ... ); ``` [code link](https://github.com/efabless/caravel_mgmt_soc_litex/blob/mpw-8c/verilog/rtl/mgmt_core_wrapper.v#L173C1-L174C33) #### mgmt_core.v - RSTB -> resetb -> rstb_h -> rstb_l -> [rstb_l_in -> rstb_l_out] -> rstb_l_buf ``` module mgmt_core( ... input wire rstb_l_in, output wire rstb_l_out, ... ); ... assign rstb_l_out = rstb_l_in; ... endmodule ``` [code link](https://github.com/efabless/caravel_mgmt_soc_litex/blob/main/verilog/rtl/mgmt_core.v#L1823C1-L1823C31) ## trace resetb_core_h signal ### caravel.v ``` module caravel ( ... input resetb, ... ); ... wire rstb_h; chip_io padframe( ... ... .resetb_core_h(rstb_h), //O ... ); ``` [resetb link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L61) [rstb_h link](https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L372) ### chip_io.v https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/chip_io.v#L64 ``` module chip_io( ... output resetb_core_h, ... ); ``` https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/chip_io.v#L299-L323 ``` sky130_fd_io__top_xres4v2 resetb_pad ( `MGMT_ABUTMENT_PINS `ifndef TOP_ROUTING .PAD(resetb), `endif ... .XRES_H_N(resetb_core_h), ... ); ``` [Tony] resetb_core_h -> rstb_h -> rstb_l https://github.com/efabless/caravel/blob/mpw-8c/verilog/rtl/caravel.v#L1583-L1593 ``` // XRES (chip input pin reset) reset level converter xres_buf rstb_level ( `ifdef USE_POWER_PINS .VPWR(vddio_core), .LVPWR(vccd_core), .LVGND(vssd_core), .VGND(vssio_core), `endif .A(rstb_h), .X(rstb_l) ); ``` # caravel_rstn - RSTB -> resetb -> rstb_h -> rstb_l -> rstb_l_buf ``` caravel_clocking clock_ctrl ( ... .resetb(rstb_l_buf), //input ... .ext_reset(ext_reset), // From housekeeping SPI ... .resetb_sync(caravel_rstn) //output ); ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/caravel.v#L763C8-L763C35) ## caravel_clocking.v - RSTB -> resetb -> rstb_h -> rstb_l -> rstb_l_buf -> resetb -> resetb_async -> resetb_sync ``` module caravel_clocking( ... input porb, // Master (negative sense) reset from power-on-reset input resetb, // Master (negative sense) reset ... input ext_reset, // Positive sense reset from housekeeping SPI. ... output resetb_sync // Output propagated and buffered reset ); ... assign resetb_async = porb & resetb & (!ext_reset); ... // Staged-delay reset reg [2:0] reset_delay; always @(negedge core_clk or negedge resetb_async) begin if (resetb_async == 1'b0) begin reset_delay <= 3'b111; end else begin reset_delay <= {1'b0, reset_delay[2:1]}; end end assign resetb_sync = ~reset_delay[0]; ... endmodule ``` [code link]() ``` module caravel_clocking( `ifdef USE_POWER_PINS input VPWR, input VGND, `endif input porb, // Master (negative sense) reset from power-on-reset input resetb, // Master (negative sense) reset input ext_clk_sel, // 0=use PLL clock, 1=use external (pad) clock input ext_clk, // External pad (slow) clock input pll_clk, // Internal PLL (fast) clock input pll_clk90, // Internal PLL (fast) clock, 90 degree phase input [2:0] sel, // Select clock divider value (0=thru, 1=divide-by-2, etc.) input [2:0] sel2, // Select clock divider value for 90 degree phase divided clock input ext_reset, // Positive sense reset from housekeeping SPI. output core_clk, // Output core clock output user_clk, // Output user (secondary) clock output resetb_sync // Output propagated and buffered reset ); ``` [code link](https://github.com/efabless/caravel-lite/blob/main/verilog/rtl/caravel_clocking.v#L19C1-L36C3) # management protect ``` module mgmt_protect ( ... ); mprj_logic_high mprj_logic_high_inst ( `ifdef USE_POWER_PINS .vccd1(vccd1), .vssd1(vssd1), `endif .HI(mprj_logic1) //output ); endmodule ``` [code link](https://github.com/efabless/caravel-lite/blob/mpw-8c/verilog/rtl/mgmt_protect.v#L126C1-L132C11) ## module mprj_logic_high ``` module mprj_logic_high ( `ifdef USE_POWER_PINS inout vccd1, inout vssd1, `endif output [462:0] HI ); sky130_fd_sc_hd__conb_1 insts [462:0] ( `ifdef USE_POWER_PINS .VPWR(vccd1), .VGND(vssd1), .VPB(vccd1), .VNB(vssd1), `endif .HI(HI), //output .LO() //output ); endmodule ``` [code link](https://github.com/efabless/caravel-lite/blob/main/verilog/rtl/mprj_logic_high.v#L16C1-L21C22) ``` module sky130_fd_sc_hd__conb_1 ( HI , LO , VPWR, VGND, VPB , VNB ); output HI ; output LO ; input VPWR; input VGND; input VPB ; input VNB ; sky130_fd_sc_hd__conb base ( .HI(HI), .LO(LO), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB) ); endmodule ``` [code link](https://raw.githubusercontent.com/efabless/caravel_mgmt_soc_litex/mpw-8c/verilog/cvc-pdk/sky130_fd_sc_hd.v)