---
tags: computer-arch
---
# Computer Architecture 2024: Term Project
> :notebook: You must provide the materials and demonstrate to the lecturer before ==Jan 23, 2025==
## Fill in the table for your term project
> * Send email to `<jserv.tw@gmail.com>` to confirm the details and expectations.
> * Numbers denote the expected sizes of the teams, and you should replace them with your name(s) if you are about to take the task.
> * Reference: [Terms projects for 2023](https://hackmd.io/@sysprog/arch2023-projects), [Terms projects for 2022](https://hackmd.io/@sysprog/arch2022-projects), [Terms projects for 2021](https://hackmd.io/@sysprog/arch2021-projects)
| Group | Topic | HackMD note |
|:-------------------------- | ----- | --------------- |
| 陳孟鴻 | rv32emu system emulation via JIT compilation | [rv32emu](https://hackmd.io/@sysprog/r1e60140Vyl) |
| 林志懋 | superscalar out-of-order 64-bit RISC-V core capable of booting Linux | [soomrv64](https://hackmd.io/@sysprog/HyErZNAEJg) |
| 林子齊 | 5-stage pipelined RISC-V processor capable of running FreeRTOS | [pipelined-processor](https://hackmd.io/@sysprog/SkW7GECVJx) |
| 邱繼寬 | Fast usermode x86-64 emulator for RISC-V | [box64](https://hackmd.io/@sysprog/ryZfQVCN1l) |
| 黃啟維 | Matrix Multiplication Accelerator implemented with Chisel | [matmul](https://hackmd.io/@sysprog/BkIuQE0E1g) |
| 蔡承璋, 張恩祥 | 5-stage pipelined RISC-V processor with RV32IMC | [pipelined-processor](https://hackmd.io/@sysprog/SkTjS4ANyl) |
| 林濤 | Digital signal processing and Optimization | [dsp](https://hackmd.io/@sysprog/SkzswE0Eye) |
| 洪至謙, 曾遠哲 | RVV-accelerated Image Codec | [qoi-rvv](https://hackmd.io/@sysprog/HJoJ54RVyg) |
| 陳昭詣, 周姵彣 | Port xv6-riscv to 32-bit RV32I core | [xv6-rv32i](https://hackmd.io/@sysprog/BJPdjVCNJe) |
| 曹為廷 | Annotate and explain Quiz 1 to 5 | [quiz1to5](https://hackmd.io/@sysprog/HJKRbSAVJl) |
| 章元豪 | Extend tiny-gpu | [tinygpu](https://hackmd.io/@sysprog/HkGQQHA4Jg) |
| 洪翊碩 | Convolutional Neural Network Accelerator implemented in Chisel | [cnn-accel](https://hackmd.io/@sysprog/ByIdVr04ye) |
| 姜冠宇 | 3-stage pipeplined RV32 core with B extension | [rv32b](https://hackmd.io/@sysprog/BkWFBHAVJl) |
| 陳乃宇, 陳冠霖 | Implement Vector extension for rv32emu | [rv32emu-rvv](https://hackmd.io/@sysprog/HJ7fcrC4yg) |
| 許翰翔, 簡德彥, 吳秉宥 | Implement dynamic branch prediction for pipelined RISC-V processor | [dynamic-branch-prediction](https://hackmd.io/@sysprog/BJOA9BCVkl) |
| 李宗翰, 洪靖睿 | RVV-accelerated Audio Codec | [qoa-rvv](https://hackmd.io/@sysprog/rJEa1UC4yg) |
| 陳禹丞 | Refine system emulation for rv32emu | [rv32emu-sys](https://hackmd.io/@sysprog/rkiothUSJl) |
| 陳榮昶, 林晉德 | Implement cache system for srv32 | [srv32-cache](https://hackmd.io/@sysprog/SyPRqhLBye) |
| 黃若綾, 蔡雅彤, 林靖婷 | Extend PicoRV32 | [picorv32](https://hackmd.io/@sysprog/BkCV7MDSyg) |
| 蘇暐倫 | Rework Neural Networks with low bit weights on Venus | [nn-venus](https://hackmd.io/@sysprog/Bky8cMDBkx) |
| 蘇湘婷 | WebAssembly based Linux/RISC-V System Emulation | [rv32emu-wasm](https://hackmd.io/@sysprog/B1NbJQwrJx) |
| 唐文駿 | Execution visualization for rv32emu | [rv32emu-vis](https://hackmd.io/@sysprog/Syi8MmPrke) |
| 王景霈, 傅孟楷 | Multi-threading on top of 'Operating System in 1,000 Lines' | [threading](https://hackmd.io/@sysprog/BJBqnuPBye) |
| 劉益祥 | Optimization Design of CORDIC Algorithm | [cordic](https://hackmd.io/@sysprog/HJJ5AuDSJx) |
| 余紹桓, 郭子敬 | Performance tuning for Quake/rv32emu | [quake](https://hackmd.io/@sysprog/H1sbeqPSye) |
| 陳彥廷 | RV32IM core running FreeRTOS | [rv32-rtos](https://hackmd.io/@sysprog/r1UHS9DHkg) |
| 黎詠哲, 李協儒 | Dynamic library support for shecc | [shecc](https://hackmd.io/@sysprog/BkLAU1drJe) |
| 陳致翰, 孫禾洵 | Enhance visualized RISC-V simulation | [emulsiV](https://hackmd.io/@sysprog/H1hH_y_Syx) |
| 王彥珽 | RV32IMC core | [rv32imc](https://hackmd.io/@sysprog/BJa_GxOHJx) |
| 丁語婕, 鄭煦霖, 王信智 | FreeRTOS SMP | [freertos-smp](https://hackmd.io/@sysprog/HkGawlOH1g) |
| 黃詠筑, 劉欣宜 | Build RISC-V Instruction Set Simulator from scratch | [simulator](https://hackmd.io/@sysprog/HyoeCOcr1e) |
| 林趺菩 | Evaluate NucleusRV | [NucleusRV](https://hackmd.io/@sysprog/S1cNgtqSJe) |
| 陳柏儒 | Speed up rv32emu interpreter | [rv32emu-int](https://hackmd.io/@sysprog/SJVgfF5Byg) |
| 程品叡, 吳睿秉 | Cache system for NucleusRV | [cache](https://hackmd.io/@sysprog/BJYvro9rkl) |
| 謝廷昇, 王晴文 | Accelerate Fast Fourier Transform | [fft](https://hackmd.io/@sysprog/SyOR1hqHkx) |
| 鄭九彰 | rv32 core | [rv32](https://hackmd.io/@sysprog/rJ9Z4KirJx) |
| 黃士昕 | Implement Vector extension for rv32emu | [rv32emu-rvv](https://hackmd.io/@sysprog/ByZpIYiHJg) |
| 郭君瑋 | ChiselRiscV | [rvcore](https://hackmd.io/@sysprog/B17idojHJl) |
| 阮祈翰 | Improve window system for RISC-V | [window](https://hackmd.io/@sysprog/SyrnTajr1g) |
| 蔡文賓 | Improve rv32emu performance | [rv32emu-perf](https://hackmd.io/@sysprog/Sk43eRoSyx) |
| 徐崇智, 邱家浩, 林育丞 | RISC-V Hypervisor | [hypervisor](https://hackmd.io/@sysprog/HJ7FzRiSJx) |
| 郭昱辰, 簡子昕 | Pixel-art scaling Accelerator in Chisel | [pixelart](https://hackmd.io/@sysprog/r1cybDhSye) |
| 侯廷錡 | Evaluate tiny-gpu | [tiny-gpu](https://hackmd.io/@sysprog/ByIbdK2SJl) |
| 湯秉翰 | 5-Stage Pipeline Processor in Chisel | [pipeline](https://hackmd.io/@sysprog/HyRaYtnSJl) |
| 宋唯廷, 劉孟璋 | RV32C support for srv32 | [rv32c](https://hackmd.io/@sysprog/HyW0x9nS1x) |
| 吳哲郁 | Minimal RISC-V core to boot Linux | [linux](https://hackmd.io/@sysprog/SkvKPqnH1g) |
| 饒胤琛 | Pipelined RISC-V in Chisel | [pipeline](https://hackmd.io/@sysprog/Hkh1t9hSkg) |
| 賴傑南 | Construct RISC-V in Chisel | [rvcore](https://hackmd.io/@sysprog/BJV_ZH0Skx) |
| 邱柏穎, 黃詩哲 | Branch prediction for 5-stage pipelined RISC-V | [branch-predict](https://hackmd.io/@sysprog/SJTSoPl8yx) |
| 蕭郁霖, 徐向廷 | Construct RISC-V in Chisel | [rvcore](https://hackmd.io/@sysprog/BkDHTDgU1g) |
| 李懿宸 | Evaluate BitNet inference | [bitnet](https://hackmd.io/@sysprog/S18sJdgIkg) |
| 陳侯華 | AES Implementation in Chisel | [aes-chisel](https://hackmd.io/@sysprog/B10iX_eLyg) |
| 葉人豪 | Cache simulation and case study | [cache](https://hackmd.io/@sysprog/r1Yxu_lLJg) |
| 曾謙文 | Annotate and explain Quiz6 and 7 with additional challenge Problems | [quiz67](https://hackmd.io/@sysprog/ry9ZY_xUJg) |
| 蔡承遠, 郭晏愷 | Implement RV32F | [rv32f](https://hackmd.io/@sysprog/HkkE0ueL1x) |
| 蕭維昭, 吳柏漢 | Extend riscv-mini | [riscv-mini](https://hackmd.io/@sysprog/SJCkB5lU1g) |
| 莊易騰 | SMP OS Kernel for RISC-V | [smp-os](https://hackmd.io/@sysprog/rkaLw5lI1x) |
| 黃書堯 | Optimize sqrtf without FPU | [sqrtf](https://hackmd.io/@sysprog/B1DvCcx81x) |
| 吳彥廷 | Trace and Analyze Memory Allocators in FreeRTOS | [mem](https://hackmd.io/@sysprog/r18GZoxUJe) |
| 李建佑 | Evaluate KianV | [KianV](https://hackmd.io/@sysprog/rJ7E0hl8ye) |
| 廖奕凱 | Vectorize Quite OK YCbCr420A | [qoy-rvv](https://hackmd.io/@sysprog/r1ORz6lIke) |
| 方榮彬, 龔祐萱 | Hardware Generator for JPEG Compression | [jpeg](https://hackmd.io/@sysprog/rkK8O1fLkg) |
| 傅信豪 | Hardware Ray Tracer Datapath | [raytracer](https://hackmd.io/@sysprog/SyPS6yGIyx) |
| 李尚宸 | Single-cycle RISC-V core | [rvcore](https://hackmd.io/@sysprog/S1-dkeGLyg) |
| 盧尚毅 | 5-stage pipeline RISC-V core | [pipeline](https://hackmd.io/@sysprog/HyMbMgGLkl) |
| 吳中玄 | Minimal OS Kernel for RISC-V | [os](https://hackmd.io/@sysprog/r1eb4gfL1x) |
| 蕭力文 | single-cycle RISC-V | [rvcore](https://hackmd.io/@sysprog/rJsj2gfLJe) |
| 劉哲維 | 5-stage pipeline RISC-V core | [pipeline](https://hackmd.io/@sysprog/Sy2Lz-zI1x) |
| 陳奕嘉 | Case Study on Performance Improvements | [perf](https://hackmd.io/@sysprog/SJ4fEZG8ye) |
| 章劉軒瑋 | Custom RISC-V instructions to Accelerate LLM Inference | [custom](https://hackmd.io/@sysprog/Bym6n6X8kx) |
| 柳嘉祐 | 5-stage pipeline RISC-V core | [rvcore](https://hackmd.io/@sysprog/r1jtY8UUkl) |
| 王韻茨, 王柏皓 | Implement RISC-V core | [rvcore](https://hackmd.io/@sysprog/H1kwdEFLJe) |
| 戴均原 | Pipelined RISC-V core | [pipeline](https://hackmd.io/@sysprog/rkWluEYUJg) |
| 李皓翔 | Pipelined RISC-V core | [pipeline](https://hackmd.io/@sysprog/rJ0rFNYIyg) |
| 黃守維 | RV32 support for Tina coroutine | [coroutine](https://hackmd.io/@sysprog/S1HXEIt8Jg) |
| 陳家揚 | Ethernet device implemented in Chisel | [eth](https://hackmd.io/@sysprog/HJDRLOYLye) |
| 黃灝 | Cache simulation for various matrix operations | [cache](https://hackmd.io/@sysprog/S1ygDDRLJg) |
| 李漢德 | Multithreading for RISC-V | [threads](https://hackmd.io/@sysprog/BkK6FkzPJl) |
| 黃丞漢, 江冠德 | Pipelined RISC-V core with RV32IMZbaZbbZbcZbs | [rv32imb](https://hackmd.io/@sysprog/r11x-eGDJx) |