Computer Archiecture 2023: Term Project

You must provide the materials and demonstrate to the lecturer before Jan 14, 2024

Fill in the table for your term project

• Send email to <[e-mail]> to confirm the details and expectations.
• Numbers denote the expected sizes of the teams, and you should replace them with your name(s) if you are about to take the task.
• New items MUST NOT be added. Instead, you should just provide your name(s) and any relevant hyperlinks to your progress.
• Pay attention to spacing: separate each item with |. This means there should be exactly two single space characters both before and after the | character.
• Reference: Terms projects for 2022, Terms projects for 2021

Group (add your name here)	Topic	Your Hyperlinks
1 (林晉宇)#	Rewrite Lab3 as 5-stage pipeline RISC-V processor	Rewrite Lab3 as 5-stage pipeline RISC-V processor
1 (黃于睿)#	Extend Lab3 to comply with RV32IM and CSR	Extend Lab3 to comply with RV32IM and CSR
1 (李冠澄)#	Adapt riscv-mini	Adapt riscv-mini
1+ (張智惟, 曾鼎棊, 張偉治)	Extend Lab3 to comply with Vector extension	Extend Lab3 to comply with Vector extension
1+ (李承泰, 洪碩星)	Rewrite Lab3 as 3-stage pipeline RISC-V processor with branch predictor	Rewrite Lab3 as 3-stage pipeline RISC-V processor with branch predictor
2+ (張澤家, 鍾沅熹, 侯廷翰)#	Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s) for reviewing. Reference	Contribute to Ripes
1+ (倪英智, 陳金諄)	Analyze femtorv-quark and ensure RV32IM compatibility Reference1, Reference2, Reference3	Analyze femtorv-quark and ensure RV32IM compatibility
1 (黃定山)#%	Implement A (atomic) extension for srv32MIT and verify with FreeRTOS Reference	Implement A (atomic) extension for srv32MIT and verify with FreeRTOS
1+ (陳彥佑)	Implement Vector extension for rv32emu	Implement Vector extension for rv32emu
1+ (周育晨)	Implement Vector extension for rv32emu	Implement Vector extension for rv32emu
1+ (洪佑杭, 陳浩文)	Improve RISC-V system emulation of semu Reference1	Improve RISC-V system emulation of semu
1+ (江冠霆)#	Improve rv32emu performance Reference1, Reference2, Reference3	Improve rv32emu performance
1+ (施宇庭)	Rework Homework 3	Rework Homework 3
1 (林允顥)#	Implement Linux userspace RV32 emulation for RVVM Reference	RV32_RVVM
1 (王豊惟)#	Integrate RISCOF + RISC-V Architecture Tests for RVVM Reference	Integrate RISCOF + RISC-V Architecture Tests for RVVM
1+ (林昊霆)	Study tinygpus (Make your own graphics hardware!)	tinygpus
1+ 施柏安#	Study XGSoC (FPGA based system on chip with audio, video and 3D acceleration) and ensure simulation functionality by integrating more samples Reference	Study XGSoC (FPGA based system on chip with audio, video and 3D acceleration) and ensure simulation functionality by integrating more samples
1+ 陸品潔 唐飴苹	Study Minimax (Compressed-First, Microcoded RISC-V core). Use FuseSOC for somulation. Reference	Study Minimax (Compressed-First, Microcoded RISC-V core)
1+ (廖泓博, 陳川曜)	Implement MMU for mini-rv32ima to boot xv6 or Linux Reference1, Reference2, Reference3	Implement MMU for mini-rv32ima to boot xv6 or Linux
1 (陳燦仁)	Study PicoRV32 and add custom instructions which can be recognized/manipulated by the processor Reference	PicoRV32
1+ (謝維倫)	Adapt/Rewrite a non-trival application in RISC-V assembly, running on Ripes	Adapt/Rewrite a non-trival application in RISC-V assembly, running on Ripes
2+ 鄭吉廷, 李亮穎	Cache simulation and case study Reference1, Reference2, Reference3	Cache simulation and case study
1 (洪胤勛)	Optimize QR code generation programs (tweaked for srv32, RV32IM) Reference1, Reference	Optimize QR code generation programs
1+ (丁竟烽, 李熙堃)	Improve JPEG Encoder (tweaked for rv32emu) Reference	Improve JPEG Encoder (tweaked for rv32emu)
1+ (彭煜博, 李晨瑞)	RV32 port for MIT xv6 operating system (and contribute!) Rerefence1, Reference2, Reference3, Reference4, Reference5	RV32 port for MIT xv6 operating system
1+ 楊宇翔 蕭明祥	Implement RISC-V pipelined processor from scratch Reference1, Reference2, Reference3	Implement RISC-V pipelined processor from scratch
1+ (高紹捷, 簡志耀, 黃柏叡)	Study RISCV-Atom (32-bit embedded-class RISC-V processor) and implement RV32M Reference	RISCV-Atom (32-bit embedded-class RISC-V processor) and implement RV32M
1 (劉智恩)	Annotate and explain Quiz1/2/3 with Ripes simulation	Quiz1/Quiz2/Quiz3
1 (吳堉銨)#	Annotate and explain Quiz4/5 with additional challenge Problems	Annotate and explain Quiz4/5 with additional challenge Problems
1 (顏伯丞)#	Annotate and explain Quiz6/7 with additional challenge Problems	Quiz6/Quiz7
1 (范紘維)#	Annotate and explain Quiz7 + Problem G (cache coherence simulation)	Annotate and explain Quiz7 + Problem G (cache coherence simulation)
1 (林柏全)	Rework Homework1	Rework Homework1
1 (張正德)	Rework Homework3	Rework Homework3
1+ (盧俊銘, 魏泳禎)	Port FreeRTOS on femtorv and prepare showcase Reference, [Reference2]	Port FreeRTOS on femtorv and prepare showcase
1 (鄭朝駿)	Validate the pipeline design of kleine-riscv and Implement RV32M Reference	Analyze the pipeline design of kleine-riscv and Implement RV32M
1 (許唯萱)	Analyze rv32emu	Analyze rv32emu
1 (陳冠元)#	Adapt QR code generation program on lab3 Reference1, Reference	Adapt QR code generation program on lab3
1 (魏彥庭)#	Implement computer vision algorithms with RISC-V Vector extension	Implement computer vision algorithms with RISC-V Vector extension
1 (戴鈞彥)	Implement Vector extension for RVVM	Implement Vector extension for RVVM
1 (林勁羽)#	Consolidate Homework3	Consolidate Homework3
1 (鄭博文)	Enhance DCT (discrete cosine transform) kernel function, RV32IM (w/ Fixed-point Arithmetic)	Enhance DCT (discrete cosine transform) kernel function, RV32IM (w/ Fixed-point Arithmetic)
1 (蔡忠翰)	Extend Homework3 to 3-stage pipeline processor	Extend Homework3 to 3-stage pipeline processor
1 (林子勝)	Adapt a non-trivial application running on MyCPU (Homework3)	Adapt a non-trivial application running on MyCPU (Homework3)

Pay attention to spacing: separate each item with |. This means there should be exactly two single space characters both before and after the | character.