--- tags: computer-arch --- # Computer Archiecture 2023: Term Project > :notebook: You must provide the materials and demonstrate to the lecturer before ==Jan 14, 2024== ## Fill in the table for your term project > * Send email to `<jserv.tw@gmail.com>` to confirm the details and expectations. > * Numbers denote the expected sizes of the teams, and you should replace them with your name(s) if you are about to take the task. > * **New items MUST NOT be added**. Instead, you should just provide your name(s) and any relevant hyperlinks to your progress. > * Pay attention to spacing: separate each item with `|`. This means there should be exactly two single space characters both before and after the `|` character. > * Reference: [Terms projects for 2022](https://hackmd.io/@sysprog/arch2022-projects), [Terms projects for 2021](https://hackmd.io/@sysprog/arch2021-projects) | Group (add your name here) | Topic | Your Hyperlinks | |:-------------------------- | ----- | --------------- | | 1 (林晉宇)# | Rewrite Lab3 as 5-stage pipeline RISC-V processor | [Rewrite Lab3 as 5-stage pipeline RISC-V processor](https://hackmd.io/@linyu0425/SJZS-LWtp) | | 1 (黃于睿)# | Extend Lab3 to comply with RV32IM and CSR | [Extend Lab3 to comply with RV32IM and CSR](https://hackmd.io/@DarrenHuang0411/CA_Final_Project)| | 1 (李冠澄)# | Adapt [riscv-mini](https://github.com/ucb-bar/riscv-mini) | [Adapt riscv-mini](https://hackmd.io/@Kuanch/H1aJnFBLp) | | 1+ (張智惟, 曾鼎棊, 張偉治) | Extend Lab3 to comply with Vector extension | [Extend Lab3 to comply with Vector extension](https://hackmd.io/@scottgood333/HJyoSYMup) | | 1+ (李承泰, 洪碩星) | Rewrite Lab3 as 3-stage pipeline RISC-V processor with branch predictor | [Rewrite Lab3 as 3-stage pipeline RISC-V processor with branch predictor](https://hackmd.io/@shhung/Syfu0Z3Ip) | | 2+ (張澤家, 鍾沅熹, 侯廷翰)# | Contribute to [Ripes](https://github.com/mortbopet/Ripes/issues): pick up pending issues, work on them, and finally send pull request(s) for reviewing.<br> [Reference](https://hackmd.io/@Rwbh0z6QRXqUP7ovs7txiQ/HySbbdSCw) | [Contribute to Ripes](https://hackmd.io/@NeedSleep/CA_Final) | | 1+ (倪英智, 陳金諄) | Analyze [femtorv-quark](https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV) and ensure RV32IM compatibility <br> [Reference1](https://twitter.com/BrunoLevy01/status/1597349972462432256), [Reference2](https://hackmd.io/@N9qHU_eLRvKyfDfJk8cDXA/Byj08q3jK), [Reference3](https://hackmd.io/@Fo7UsdePRsKPVV4CPYGbpA/ryyNduFFo) | [Analyze femtorv-quark and ensure RV32IM compatibility](https://hackmd.io/@david96514/Hyt2ycWOa) | | 1 (黃定山)#% | Implement A (atomic) extension for [srv32](https://github.com/kuopinghsu/srv32)^MIT^ and verify with FreeRTOS <br> [Reference](https://hackmd.io/@P31nISeeTvau1gKumIykRA/SJ3LH14aF) | [Implement A (atomic) extension for srv32^MIT^ and verify with FreeRTOS](https://hackmd.io/1R4NwdVJQXy2zskvnSZ8mA?view) | | 1+ (陳彥佑) | Implement [Vector extension](https://github.com/riscv/riscv-v-spec) for [rv32emu](https://github.com/sysprog21/rv32emu) | [Implement Vector extension for rv32emu ](https://hackmd.io/bPvis8e3RiaFAdHuFmWskg) | | 1+ (周育晨) | Implement [Vector extension](https://github.com/riscv/riscv-v-spec) for [rv32emu](https://github.com/sysprog21/rv32emu) | [Implement Vector extension for rv32emu](https://hackmd.io/eA-4w5LAQsenZwWqx8dGJw?view) | | 1+ (洪佑杭, 陳浩文) | Improve RISC-V system emulation of [semu](https://github.com/sysprog21/semu) <br> [Reference1](https://gitlab.com/luplab/lupv) | [Improve RISC-V system emulation of semu](https://hackmd.io/@hungyuhang/risc-v-term-project) | | 1+ (江冠霆)# | Improve [rv32emu](https://github.com/sysprog21/rv32emu) performance<br> [Reference1](https://github.com/sysprog21/rv32emu/issues/88), [Reference2](https://github.com/sysprog21/rv32emu/issues/283), [Reference3](https://hackmd.io/@qwe661234/S1XQAExti) | [Improve rv32emu performance](https://hackmd.io/@VBHMCAcXSo2j5UzcTBAQZQ/S1r7KlpuT) | | 1+ (施宇庭) | <!-- Improve [rv32emu](https://github.com/sysprog21/rv32emu) correctness<br> [Reference1](https://github.com/sysprog21/rv32emu/issues/258) --> Rework Homework 3 | [Rework Homework 3](https://hackmd.io/@yutingshih/ca2023-final) | | 1 (林允顥)# | Implement Linux userspace RV32 emulation for [RVVM](https://hackmd.io/@huang-me/ca_rvvm)<br> [Reference](https://hackmd.io/@huang-me/ca_rvvm) | [RV32_RVVM](https://hackmd.io/@fewletter/RV32_RVVM) | | 1 (王豊惟)# | Integrate RISCOF + RISC-V Architecture Tests for [RVVM](https://hackmd.io/@huang-me/ca_rvvm)<br> [Reference](https://hackmd.io/@huang-me/ca_rvvm) | [Integrate RISCOF + RISC-V Architecture Tests for RVVM](https://hackmd.io/@mlFpoYoxSjevnbdVLdrijw/rvvm-riscof) | | 1+ (林昊霆) | Study [tinygpus](https://github.com/sylefeb/tinygpus) (Make your own graphics hardware!) | [tinygpus](https://hackmd.io/@TBL/SyAlpBlKT) | | 1+ 施柏安# | Study [XGSoC](https://github.com/dcliche/xgsoc) (FPGA based system on chip with audio, video and 3D acceleration) and ensure simulation functionality by integrating more samples<br> [Reference](https://hackmd.io/@y8jRQNyoRe6WG-qekloIlA/HJOF9Nuui) | [Study XGSoC (FPGA based system on chip with audio, video and 3D acceleration) and ensure simulation functionality by integrating more samples](https://hackmd.io/@brianPA/Skv2HO-Dp) | | 1+ 陸品潔 唐飴苹 | Study [Minimax](https://github.com/gsmecher/minimax) (Compressed-First, Microcoded RISC-V core). Use FuseSOC for somulation.<br> [Reference](https://news.ycombinator.com/item?id=33422717) | [Study Minimax (Compressed-First, Microcoded RISC-V core)](https://hackmd.io/@O6C2C3zQQBanDM55QRZ7DQ/study_minimax) | | 1+ (廖泓博, 陳川曜) | Implement MMU for [mini-rv32ima](https://github.com/cnlohr/mini-rv32ima) to boot xv6 or Linux<br> [Reference1](https://github.com/jserv/semu), [Reference2](https://github.com/qqgnoe466263/rv32-emu), [Reference3](https://youtu.be/YT5vB3UqU_E) | [Implement MMU for mini-rv32ima to boot xv6 or Linux](https://hackmd.io/@nckuee-finalproject/CA_Final_Project)| | 1 (陳燦仁)| Study [PicoRV32](https://github.com/YosysHQ/picorv32) and [add custom instructions](https://github.com/uki-a/custom-riscv) which can be recognized/manipulated by the processor<br> [Reference](https://hackmd.io/@30vhEV7FQECcWeCF1eAN5A/S1ybboVnK) | [PicoRV32](https://hackmd.io/@TRChen/Hko56ONd6) | | 1+ (謝維倫) | Adapt/Rewrite a non-trival application in RISC-V assembly, running on Ripes | [Adapt/Rewrite a non-trival application in RISC-V assembly, running on Ripes](https://hackmd.io/@VCNgJgo3RCyrEhvI9NKLUQ/BychrXYO6) | | 2+ 鄭吉廷, 李亮穎 | Cache simulation and case study<br> [Reference1](https://hackmd.io/@AOmdVHgtTeW-V72uCBTjTw/rkfoi17Tt), [Reference2](https://hackmd.io/@r1YLxwFRRPe1xninh0Ma6w/SJRrVgQcj), [Reference3](https://hackmd.io/@zKOCm3SSTKyUyiPV-nfEjw/ByyIBzzuo) | [Cache simulation and case study](https://hackmd.io/yOQ-XjR6TA2i-Qh7GsOtNw?both) | | 1 (洪胤勛) | Optimize [QR code generation](https://www.nayuki.io/page/creating-a-qr-code-step-by-step) programs (tweaked for [srv32](https://github.com/kuopinghsu/srv32), RV32IM)<br> [Reference1](https://github.com/sysprog21/rv32emu/blob/master/tests/qrcode.c), [Reference](https://github.com/fabiankuffer/RISC-V-QR-Code-Generator) | [Optimize QR code generation programs](https://hackmd.io/@KXkA4u0LQuyNTwOorDw2RA/Skg-yOGua) | | 1+ (丁竟烽, 李熙堃)| Improve JPEG Encoder (tweaked for rv32emu)<br> [Reference](https://github.com/lorenz369/JPEG_Encoder) | [Improve JPEG Encoder (tweaked for rv32emu)](https://hackmd.io/@JoshuaLee0321/Improve_JPEG_Encode) | | 1+ (彭煜博, 李晨瑞) | RV32 port for [MIT xv6 operating system](https://github.com/mit-pdos/xv6-riscv) (and contribute!)<br>[Rerefence1](https://www.uni-bamberg.de/fileadmin/sysnap/slides/xv6-riscv.pdf), [Reference2](https://github.com/harihitode/ladybird-xv6), [Reference3](https://ithelp.ithome.com.tw/m/users/20138181/ironman/5395), [Reference4](https://www.youtube.com/user/hhp3/videos), [Reference5](https://hackmd.io/@ihvNzfsUS1GqCZHdnD-iWw/HJu_RZs5j) | [RV32 port for MIT xv6 operating system](https://hackmd.io/@terry23304/HJC5O6A0h) | | 1+ 楊宇翔 蕭明祥 | Implement RISC-V pipelined processor from scratch<br> [Reference1](https://github.com/Ellllipse/RISCV-processor-design), [Reference2](https://hackmd.io/@kaminto-1999/final-project), [Reference3](https://hackmd.io/@CWWPPB/S1HVmuvuo) | [Implement RISC-V pipelined processor from scratch](https://hackmd.io/jQ4yP94_Sv6y85JBiH5Amw?view) | | 1+ (高紹捷, 簡志耀, 黃柏叡) | Study [RISCV-Atom](https://github.com/saursin/riscv-atom) (32-bit embedded-class RISC-V processor) and implement RV32M <br> [Reference](https://hackmd.io/@wanghanchi/SJTRpltqj) | [RISCV-Atom (32-bit embedded-class RISC-V processor) and implement RV32M](https://hackmd.io/HdMEALKjTnSFF_d7QE3ESw?view) | | 1 (劉智恩) | Annotate and explain Quiz1/2/3 with Ripes simulation | [Quiz1](https://hackmd.io/qyJn5jcVTneEEsdZNtR_CA)/[Quiz2](https://hackmd.io/fitnLis2TlulyRSt41nFxw?view)/[Quiz3](https://hackmd.io/w-_x2rYxTnivsZyBQueSUA) | | 1 (吳堉銨)# | Annotate and explain Quiz4/5 with additional challenge Problems | [Annotate and explain Quiz4/5 with additional challenge Problems](https://hackmd.io/@c3WNnG7RRK2J17ifSiezZA/Bk1mQfKuT) | | 1 (顏伯丞)# | Annotate and explain Quiz6/7 with additional challenge Problems | [Quiz6](https://hackmd.io/@QtzWvn_wQCicLQ65E_OREQ/final-projects_Q6)/[Quiz7](https://hackmd.io/@QtzWvn_wQCicLQ65E_OREQ/final-projects_Q7) | | 1 (范紘維)# | Annotate and explain Quiz7 + Problem G (cache coherence simulation) | [Annotate and explain Quiz7 + Problem G (cache coherence simulation)](https://hackmd.io/@gV8IONkMS_a6aHt20QNuAg/rJUNzv-u6)| | 1 (林柏全) | Rework Homework1 | [Rework Homework1](https://hackmd.io/@c3qLIGuDRtWykAmg5L50Ww/CA-Final/https%3A%2F%2Fhackmd.io%2F%40c3qLIGuDRtWykAmg5L50Ww%2FCA-Final-Intro) | | 1 (張正德) | Rework Homework3 | [Rework Homework3](https://hackmd.io/@gofzKoaiTI6mFzp4FTuenw/HyPueN-tp) | | 1+ (盧俊銘, 魏泳禎) | Port FreeRTOS on [femtorv](https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV) and prepare showcase<br> [Reference](https://hackmd.io/@N9qHU_eLRvKyfDfJk8cDXA/Byj08q3jK), [Reference2] | [Port FreeRTOS on femtorv and prepare showcase](https://hackmd.io/@jimmylu0303/final-project) | | 1 (鄭朝駿) | Validate the pipeline design of [kleine-riscv](https://github.com/rolandbernard/kleine-riscv) and Implement RV32M<br>[Reference](https://hackmd.io/@HFmqOuSxQjKLe9lBinlkmw/SJgSrgQpF) | [Analyze the pipeline design of kleine-riscv and Implement RV32M](https://hackmd.io/@J7GZnFx3Qe-HPvOgHWEQsg/BJd4R-2dp) | | 1 (許唯萱) | Analyze [rv32emu](https://github.com/sysprog21/rv32emu) | [Analyze rv32emu](https://hackmd.io/@weishiuan/computer_architecture2023/edit) | | 1 (陳冠元)# | Adapt [QR code generation](https://www.nayuki.io/page/creating-a-qr-code-step-by-step) program on [lab3](https://github.com/sysprog21/ca2023-lab3) <br> [Reference1](https://github.com/sysprog21/rv32emu/blob/master/tests/qrcode.c), [Reference](https://github.com/fabiankuffer/RISC-V-QR-Code-Generator) | [Adapt QR code generation program on lab3](https://hackmd.io/@K1NCVjKnTCmNaikFb4gt-A/final-term) | | 1 (魏彥庭)# | Implement computer vision algorithms with RISC-V Vector extension |[Implement computer vision algorithms with RISC-V Vector extension](https://hackmd.io/@Terry7Wei7/final-project)| | 1 (戴鈞彥) | Implement Vector extension for RVVM | [Implement Vector extension for RVVM](https://hackmd.io/@ranvd/implement-vector-extension-for-rvvm) | | 1 (林勁羽)# | Consolidate Homework3 | [Consolidate Homework3](https://hackmd.io/@edenlin/Construct_a_Single-Cycle_RISC-V_CPU_with_Chisel) | | 1 (鄭博文) | Enhance DCT (discrete cosine transform) kernel function, RV32IM (w/ Fixed-point Arithmetic) | [Enhance DCT (discrete cosine transform) kernel function, RV32IM (w/ Fixed-point Arithmetic)](https://hackmd.io/@PWCheng/DCT) | | 1 (蔡忠翰) | Extend Homework3 to 3-stage pipeline processor | [Extend Homework3 to 3-stage pipeline processor](https://hackmd.io/@jeremytsai/computer_architecture_final_project) | | 1 (林子勝) | Adapt a non-trivial application running on MyCPU (Homework3) | [Adapt a non-trivial application running on MyCPU (Homework3)](https://hackmd.io/@zisheng/S1p_Z0PuT) | > :warning: Pay attention to spacing: separate each item with `|`. This means there should be exactly two single space characters both before and after the `|` character.
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