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Computer Archiecture 2021: Term Project

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You must provide the materials and demonstrate to the lecturer before Jan 19, 2022

Fill in the table for your term project

Send email to <jserv.tw@gmail.com> to confirm the details and expectations.
reference: Terms projects for 2020

Group (add your name here) Topic Your Hyperlinks
陳昕佑, 陳日昇 Explain how biRISC works.
biRISC is a 32-bit RISC-V ISA CPU core with superscalar (dual-issue) in-order 6 or 7 stage pipeline. You shall use Verilator to validate and discover the internals.
biRISC-V
林甄羚, 黃瑋盛, 林嘉歆 Explain how FemtoRV works and provide preliminary privileged instruction set support. FemtoRV
黃品程, 許永貞, 鄭學陽 Analyze NEORV32 and verify its internals NEORV32
劉品宏, 朱俊霖, 伍志忠, 鄒柏宇 Analyze spu32 with Yosys open synthesis suite. Explain how it works and validate it. spu32
方竫泓, 李安豐, 李其祐 Analyze minrv32 and implement compressed instruction set.
Reference: Report 2020
Analyze minrv32 and implement compressed instruction set.
劉恩澔 Implement A (atomic) extension for srv32MIT Implement A (atomic) extension for srv32MIT
蕭珮珊, 張亦妤 Analyze and improve srv32MIT Analyze and improve srv32
向景亘 Run FreeRTOS and multitasking
Reference: Report 2020
Run FreeRTOS and multitasking on VexRiscv
賴虓翰 Contribute to rv32emu-next Contribute to rv32emu-next
歐禮寬 Run Quake on rv32emu-next. Run Quake on rv32emu-next
黃上睿 Annotate and explain Quiz3 Annotate Quiz3
徐卓朗 Annotate and explain Quiz5 with Ripes simulation Annotate Quiz5
張又仁 Annotate and explain Quiz6 with Ripes simulation Annotate Quiz6
郭又宗 Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
Reference: Report 2020
Final Project: Contribute to Ripes
杰凱力艾 Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s).
Reference: Report 2020
Add example program for file I/O
歐子杰 Improve RV32I backend for shecc Improve RV32I backend for shecc
林信宇 Improve ria-jit.
Reference: Report 2020
Improve ria-jit
朱祐均 Analyze ASFRV32IM and explain how it works Fianl Project - ASFRV32IM
鄭力維 Analyze kleine-riscv and validate its pipeline design kleine-riscv: How to start & How can we learned from the design
朱育萱, 黃牧恩 Analyze RVVM and explain how Linux kernel is booted in its RV32 environment. RVVM
陳力維, 陳銘畯 Write comprehensive tutorial for WebRISC-V.
It is a web-based education-oriented RISC-V pipeline simulation environment.
term-project (WebRISC-V)
戴仕誠 Rework Homework1 Rework Homework1
莊崴 Follow How I built a RISC-V CPU Core in a span of 5 days and rework for 32-bit RISC-V Follow How I built a RISC-V CPU Core in a span of 5 days and rework for 32-bit RISC-V
陳韋綸 Analyze RISC-V Core with cache RISC-V Core
李仲恩 Study rISA and port RISC-V programs Study rISA and port RISC-V programs
陳明吉 Rework Homework3 Rework Homework3
孫祥鈞, 李政憲 Analyze PicoRV32 PicoRV32
林劭謙 Implement Eytzinger Binary Search with Ripes Implement Eytzinger Binary Search with Ripes
張峻瑋 Annotate Quiz7 Annotate Quiz7
柯凱瑋 Analyze QR-Code Generator and improve Analyze QR-Code Generator and improve
羅紹豪 Rework CacheLab Rework CacheLab