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# Follow [How I built a RISC-V CPU Core in a span of 5 days](https://github.com/iamrk-vlsi/RISC-V-MYTH-Workshop) and rework for 32-bit RISC-V
###### tags: `computer-arch-HW`
## Content
### Main plan for this term project !
* Because we want to reconstruct the RISC-V CPU core with 32-bit ISA,then we need to plan the outline about each stage of this term project, which would be showed like below!
- [ ] 1. Build the RISC-V CPU with default 64-bit ISA! (Author written)
* main motivation about this stage is that helping us to familly with the whole architecture !
- [x] 1-1. Using `RISC-V toolchain` to compile the c code we modify.(`riscv32-unknown-elf-gcc`,`riscv64-unknown-elf-gcc`)
- [x] 1-2. Using `spike` and `pk` to simulate the code compiled by `RISC-V toolchain` compiler.
- [ ] 1-3. Built `riscv64-core` by using `Makerchip`.
- [ ] 1-4. Using `iverilog` to establish the `riscv64-core` (Made by author) and execute the object file privious compiled.
- [x] 2. Make clearly knowing about where is ISA in this architecture.
* Observe the builiting processing, and then try to make clear note about the ISA position of CPU core.
- [ ] 3. Replace expected ISA to our built RISC-V CPU core!
* Main task in this term project!
- [ ] 3-1. Built our `riscv32-core` by using `Makerchip`.
- [x] 3-2. Translate the built`5-stage-rsicv64-pipline` to verilog format
- [x] 3-3. Using `iverilog` to establish the `riscv32-core` (`picorv32.v`) and execute the object file privious compiled.
## Build the RISC-V CPU with default 64-bit ISA!
### Day 1 Instruction Set Architecture & GNU Toolchain.
#### Lab 1 : C program of Sum 1 to n numbers.
* The basic concept to compile the C code by gcc compiler is like that we could using compiler by fellowing command to compile the code we writed, then the `sum1to9` (custom name) execution file would be built, we could directly exeucute this file.
```shell=
gcc -o sum1to9 sum1to9.c
./sum1to9
```
#### Lab 2 : C program of Sum 1 to n numbers, RISC-V toolchain.
* Because we need to use the RISC-V toolchain, then we install [riscv-gun-toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain) first.
* Last time we use `riscv32`, then this time we need to re-make `riscv-gun-toolchain` with 64-bits version.
```shell=
cd /home/wei/riscv-gnu-toolchain
./configure --prefix=/opt/riscv64 --with-arch=rv64imc --with-abi=lp64
sudo make
```
* After install [riscv-gun-toolchain](https://github.com/riscv-collab/riscv-gnu-toolchain), then we could add bin folder path in our `~/.bashrc file`. Help us initialize the enviroment when we create new terminal.
```shell=
vim ~/.bashrc # add new path in .bashrc file!
cat ~/.bashrc
```
* Start compile the code by using the riscv-gun-toolchain. (for 64-bits)
```shell=
riscv64-unknown-elf-gcc -O1 -mabi=lp64 -march=rv64i -o sum1to9_64.o sum1to9.c
# using O1 optimization level and with rv64i architecture, abi for l->long, p->pointer data type using 64-bits.
```
* The consequence like this, we get the `sum1to9_64.o` from `riscv64-unknown-elf-gcc` compiler.
* some discription of `-mabi` from document!
-mabi=ABI-string
Specify integer and floating-point calling convention. ABI-string contains two parts: the size of integer types and the registers used for floating-point types. **For example -march=rv64ifd -mabi=lp64d means that long and pointers are 64-bit** (implicitly defining int to be 32-bit), and that floating-point values up to 64 bits wide are passed in F registers. Contrast this with -march=rv64ifd -mabi=lp64f, which still allows the compiler to generate code that uses the F and D extensions but only allows floating-point values up to 32 bits long to be passed in registers; or -march=rv64ifd -mabi=lp64, in which no floating-point arguments will be passed in registers.
The default for this argument is system dependent, users who want a specific calling convention should specify one explicitly. The valid calling conventions are: ilp32, ilp32f, ilp32d, lp64, lp64f, and lp64d. Some calling conventions are impossible to implement on some ISAs: for example, -march=rv32if -mabi=ilp32d is invalid because the ABI requires 64-bit values be passed in F registers, but F registers are only 32 bits wide.
* Using `riscv64-unknown-elf-objdump` to read elf assemble code.
```shell=
riscv64-unknown-elf-objdump -d sum1to9_64.o
```
* Because the `spike` and `pk` simulator we don't have, then we need to install the above two tools.
* Start to install [spike](https://github.com/riscv-software-src/riscv-isa-sim)
```shell=
git clone https://github.com/riscv-software-src/riscv-isa-sim.git
cd riscv-isa-smi
sudo apt-get update
sudo apt-get install device-tree-compiler
mkdir build
cd build
../configure --prefix=$RISCV # $RISCV where your RISCV install
make
sudo make install
```
* Start to install [pk](https://github.com/riscv-software-src/riscv-pk)
```shell=
git clone https://github.com/riscv-software-src/riscv-pk.git
cd riscv-pk
mkdir build
cd build
../configure --prefix=$RISCV --host=riscv64-unknown-elf # $RISCV where your RISCV install
make
sudo make install
```
* using the `spike` and `pk` to simulate the riscv64 assemble code.
```shell=
spike pk sum1to9_64.o
```
* We could get the output directly by this simulator on terminal
* Which could be run in steps by adding `-d` with command.
```shell=
spike -d pk sum1to9_64.o
```
* When we key in the "enter", we could execute the assembly code steps by steps.
#### Lab 3 : Max and Min number representations.
* Now, we use `riscv64-unknown-elf-gcc` to compile the `unsignedHighest.c` and using `spike` and `pk` simulator to test this code.
```shell=
riscv64-unknown-elf-gcc -01 -mabi=lp64 -march=rv64i -o unsignedHighest_64.o unsignedHighest.c
spike pk unsignedHighest_64.o
```
### Day 2 Application Binary Interface and basic verification flow.
#### Lab 1 : ASM & ABI function Calls
* We still use `riscv64-unknown-elf-gcc` compiler with optimization level `Ofast` to compile it. Then we use the `riscv64-unknown-elf-objdump` to view the object file in readable format. Finally we use `spike` and `pk` simulator to test it.
```shell=
riscv64-unknown-elf-gcc -Ofast -mabi=lp64 -march=rv64i -o 1to9_custom_64.o 1to9_custom.c load.S
riscv64-unknown-elf-objdump -d 1to9_custom_64.o|less
spike pk 1to9_custom_64.o
```
* Because there are some mistake in the original code, then we need to modify the code to complete the expectance consequence.
* `1to9_custom.c`
```c=
#include <stdio.h>
extern int load(int x,int y); // remove the '.' in front of load()
int main()
{
int result=0;
int count=9;
result=load(0x0,count+1);
printf("sum of numbers from 1 to %d is %d \n",count,result);
}
```
* `load.S`
```assembly=
.section .text
.global load
.type load,@function
load:
add a4,zero,zero # initialize the a4 in zero
add a2,a1,zero # assign a1 (count+1) to a2
add a3,a0,zero # assign a0 (0x0) to a3
loop:
add a4,a3,a4 # add each element to the result
addi a3,a3,1 # update the current element by add 1 to a3
blt a3,a2,loop # check the current element if reach or not to final element
add a0,a4,zero # assign result to a0 and return it
ret # jal back to the original pc
```
* Finally we could get the terminal like below.
#### Lab 2 : To run and verify on a RISC-V Core
* Because we don't have the `riscv_workshop_collaterals`, then we decided to clone one from the github. And install the dependance.
```shell=
git clone https://github.com/kunalg123/riscv_workshop_collaterals.git
cd riscv_workshop_collaterals
cat run.sh
```
* Because we had install the `riscv64-unknown-elf-gcc`, `spike` and `pk`, then we only need to install `iverilog` in my enviroment. Comment the unnecessary part in `run.sh`
* install iverilog
```shell=
cd riscv_workshop_collaterals
sh run.sh
cd ~/iverilog
./configure
make
sudo make install
```
* Back to the `riscv_workshop_collaterals`, there are some strange about the `rv32im.sh`, because we want to exectute the `riscv64-unknown-elf-gcc`, but the `-mabi` and the `-march` are the parameter about the `riscv32`.
then I decided to re-write the `rv64im.sh` to execute, however the file `picorv32.v` is not easy to replace, because this is the core of `riscv32`, that mean I need to find out another `riscv64-core` or write new one. Of course, the `hex8tohex32.py` need to be change to `hex8tohex64.py`.
* Finally I decided to exchange the compiler to `riscv32-unknown-elf-gcc`, then using iverilog to compile `picorv32.v` and `testbench.v` this two verilog file.(means that using `riscv32-core` to execute the frimeware we previous prepare. )
* The finally output on terminal. (with the `riscv32-core` )
### Day 3 Introduction to TL Verilog and [Makerchip](https://www.makerchip.com/sandbox/).
Makerchip is the web platform to design the hardware. We could use easier HDL to describe our design, then translate to verilog. And there are lots useful function equip on the Makerchip.
#### Lab: 1 Cycle Sequential Calculator with Validity
* Copy the code in the Day3, and past on `MakerChip` .
* We could view the signal directly.
### Day 4 RISCV CPU Core Implementation.
#### Something strange I found !
* From the `riscv64-core` which author provided.
* We could find out the instructure length is't 64 bits obviously ! That means this core is `riscv32-core` not `riscv64-core` !
### Day 5 Pipelining the RISCV Core.
#### Same situation happened on 5-stage-rsicv64-pipline
* `5-stage-rsicv64-pipline`
* Translate the built `5-stage-rsicv64-pipline` to verilog format.
## Conclusion
* 1. The author had done the `riscv32-core` by using Makerchip not `riscv64-core`.
* 2. We could using `picorv32.v` to replace the core made by author.
* 3. If today we really want to use the `riscv64-core` to execute our code, then we could use [riscv-cores-list](https://github.com/riscvarchive/riscv-cores-list) to find out the core we needs.(written by verilog) But as sametime, the `hex8tohex64.py` file needs to be done first.
* 4. I had not built the own `riscv32-core`, then I use `picorv32.v` core directly.
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