2023 NCKU Computer Architecture Term Project

# 2023 NCKU Computer Architecture Term Project > contributor: <施柏安> > > reference: https://github.com/dcliche/xgsoc https://github.com/danodus/xgsoc ## Computer Info ```shell= Intel(R) Core(TM) i7-14700 28 cores ``` ## Environment Setup ``` Requirements: OSS CAD Suite (https://github.com/YosysHQ/oss-cad-suite-build) RISC-V GNU compiler toolchain for RV32IM (https://github.com/riscv-collab/riscv-gnu-toolchain) Python3 with the following PIP3 packages installed: pyserial SDL2 (for simulation only) ``` ### RISC-V GNU compiler toolchain for RV32IM I follow the steps of [LAB2](https://hackmd.io/@sysprog/SJAR5XMmi) to install GNU toolchain. The version of GNU toolchain is showing below. ![image](https://hackmd.io/_uploads/H1gGPA9FT.png) ### SDL2 Using below command to install libsdl-dev. ```shell $ sudo apt install libsdl2-dev ``` ### XGSOC I followed the steps in the [reference](https://github.com/dcliche/xgsoc). While doing the step which is copying site.template to site.mk, I changed the path in the markdown file to fit the right path like showing below. ```shell RISCV_TOOLCHAIN_PATH = /home/ubuntu20/riscv-none-elf-gcc/bin/ RISCV_TOOLCHAIN_PREFIX = riscv-none-elf- RISCV_CC_OPT = -march=rv32im -mabi=ilp32 OSS_CAD_SUITE_PATH = /home/ubuntu20/oss-cad-suite/bin/ ``` And after entering firmware directory in xgsoc, entering `make` command and got below output. ``` /home/ubuntu20/riscv-none-elf-gcc/bin/riscv-none-elf-gcc -march=rv32im -mabi=ilp32 -nostartfiles -nostdlib -Os -T firmware.ld -I ../lib start.S ../lib/io.c ../lib/sd_card.c firmware.c -o firmware.elf /home/ubuntu20/riscv-none-elf-gcc/bin/../lib/gcc/riscv-none-elf/13.2.0/../../../../riscv-none-elf/bin/ld: warning: firmware.elf has a LOAD segment with RWX permissions /home/ubuntu20/riscv-none-elf-gcc/bin/riscv-none-elf-objdump --disassemble firmware.elf > firmware.lst /home/ubuntu20/riscv-none-elf-gcc/bin/riscv-none-elf-objcopy -O binary firmware.elf firmware.bin python3 ../utils/makehex.py firmware.bin 2048 > firmware.hex ``` ## TODO: 參閱去年報告，確保 xgsoc (更新到 commit 6ff4ee5 或更晚) 得以正確用 Verilator 模擬，應當執行內附的 benchmark 並解讀數據 [去年報告](https://hackmd.io/@y8jRQNyoRe6WG-qekloIlA/HJOF9Nuui) using commit [708b694](https://github.com/danodus/xgsoc/commit/708b694e43651ce4364d1c987d840a9788f60f33) ## TODO: XGSoC 具備 set associative cache (4-way with random replacement policy)，研讀其內部設計並探討，過程中應搭配 Verilator 和 GTKwave 實際模擬，來說明其行為。注意：你可能會遇到非預期的狀況，記錄下來並嘗試排除 ## TODO: 從範例程式中，選出至少二個，從訊號和 bus 的觀點，解讀 XGSoC 的運作機制，搭配 SDL2 進行輸出和驗證 ## TODO: 嘗試修改 XGSoC 的 random replacement policy，換成其他策略並比較。