--- tags: computer-arch --- # Computer Archiecture 2022: Term Project > :notebook: You must provide the materials and demonstrate to the lecturer before ==Jan 13, 2023== ## Fill in the table for your term project > * Send email to `<jserv.tw@gmail.com>` to confirm the details and expectations. > * Numbers denote the expected sizes of the teams, and you should replace them with your name(s) if you are about to take the task. > * New items MUST NOT be added. Instead, you should just provide your name(s) and any relevant hyperlinks to your progress. > * Be aware of **spaces** while editing. > * Reference: [Terms projects for 2021](https://hackmd.io/@sysprog/arch2021-projects) | Group (add your name here) | Topic | Your Hyperlinks | |---------|---------|------------| | 1 | Implement A (atomic) extension for [srv32](https://github.com/kuopinghsu/srv32)^MIT^ and verify with FreeRTOS<br>[Reference](https://hackmd.io/@P31nISeeTvau1gKumIykRA/SJ3LH14aF) | - | | 張中龍 吳紀寬 `^` | Implement dynamic/static branch prediction for srv32^MIT^<br>[Reference](https://hackmd.io/@peishan/HkJrtKpoY) | [Implement dynamic/static branch prediction for srv32](https://hackmd.io/@ASWYWTBOSl2spdIswmr4Zw/BJJO-Un_i) | | 江坤諦 `^` | Run FreeRTOS on VexRiscv and Meature/Tweak context switch overhread<br>[Reference](https://hackmd.io/@oscarshiang/freertos_on_riscv) | [Run FreeRTOS on VexRiscv and Meature/Tweak context switch overhread](https://hackmd.io/@chiangkd/FreeRTOS-on-VexRiscv) | | 陳韋勳 `^` | Annotate and explain Quiz4/Quiz5 with Ripes simulation<br>[Reference](https://hackmd.io/@wIVnCcUaTouAktrkMVLEMA/rkm8OkOjF) | [Quiz4](https://hackmd.io/tOKEqoAAQCSI21nyTL5kmw?view) / [Quiz5](https://hackmd.io/bKpWkdbeQ6aS8KYG8EGS4g?view) | | 吳宇晨 `^` | Rework Homework1 | [rework HW1](https://hackmd.io/g_wKQHFCQT-PRrzOWGF3Vw?view)| | 何坤霖 `^` | Rework Homework3 (variant-A) | [Rework HW3](https://hackmd.io/@dgKSmDN0T_quhIoU9NVThA/rklRyCkOFo/https%3A%2F%2Fhackmd.io%2Fwgt0b13XTKu5L_SPwOpMpQ) | | 黃昱澄 `^` | Rework Homework3 (variant-B) | [rework HW3](https://hackmd.io/Not3OdaYQPmrrZcMPXU50Q?view) | | 楊淳皓 `^` | Rework Homework3 (variant-C) | [Rework HW3](https://hackmd.io/@Vgwl_uixQFasIvsDbsFlvA/risc-v-trem-proj) | | 鄭明奇 `^` | Enable sounds for [Quake video game](https://en.wikipedia.org/wiki/Quake_(video_game)) on [rv32emu](https://github.com/sysprog21/rv32emu)^MIT^ by implementing new system calls<br>[Reference](https://hackmd.io/@Korin777/HySuG17nK) | [Project : add sound of quake on rv32emu](https://hackmd.io/@teimeikichengmingchi/riscv-final-project) | | 曾晧峖 `^` | Reduce memory usage for [Doom](https://en.wikipedia.org/wiki/Doom_(1993_video_game)) running on [rv32emu](https://github.com/sysprog21/rv32emu)<br>[Reference1](https://github.com/cnlohr/embeddedDOOM), [Reference2](https://github.com/sysprog21/rv32emu/blob/master/docs/demo.md) | [Reduce memory usage for DOOM](https://hackmd.io/@tseng0201/SkVLoDgqs) | | 2+ | Analyze [minrv32](https://github.com/arghhhh/minrv32) and Consolidate RV32I/M/C (should be compliant with [riscv-tests](https://github.com/riscv-software-src/riscv-tests)).<br>Reference: [2021](https://hackmd.io/@jackli/term_project), [2022](https://hackmd.io/@horseradish1208/BkHQCN4Tv) | - | | 2+ | Contribute to [Ripes](https://github.com/mortbopet/Ripes/issues): pick up pending issues, work on them, and finally send pull request(s) for reviewing.<br>[Reference](https://hackmd.io/@Rwbh0z6QRXqUP7ovs7txiQ/HySbbdSCw) | - | | 洪嘉志 `^` | Validate the pipeline design of [kleine-riscv](https://github.com/rolandbernard/kleine-riscv) and Implement RV32M<br>[Reference](https://hackmd.io/@HFmqOuSxQjKLe9lBinlkmw/SJgSrgQpF) | [Validate the pipeline design of kleine-riscv and Implement RV32M](https://hackmd.io/@aa12551/Hka3V7Ldo) | | 鄭至崴 `^` | Analyze [femtorv-quark](https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV) and ensure RV32I compatibility<br>[Reference1](https://twitter.com/BrunoLevy01/status/1597349972462432256), [Reference2](https://hackmd.io/@N9qHU_eLRvKyfDfJk8cDXA/Byj08q3jK) | [Analyze femtorv-quark and ensure RV32I compatibility](https://hackmd.io/@Fo7UsdePRsKPVV4CPYGbpA/ryyNduFFo) | | 黃榆哲 蘇勇達 `^` | Port FreeRTOS on [femtorv](https://github.com/BrunoLevy/learn-fpga/tree/master/FemtoRV) and prepare showcase<br>[Reference](https://hackmd.io/@N9qHU_eLRvKyfDfJk8cDXA/Byj08q3jK) | [Port FreeRTOS on femtorv and prepare showcase](https://hackmd.io/@n7MIa9jgToeqs2aY5BaKEA/SyF9Oys9s) | | 2+ | Contribute to [NEORV32](https://github.com/stnolting/neorv32) (MCU-class 32-bit RISC-V soft-core CPU)<br>[Reference](https://hackmd.io/8LokWMAaTp-rvcr1B3Gqkg) | - | | 1 | Contribute RV32 support for [Tina](https://github.com/slembcke/Tina) (header only, coroutine and fiber library)<br>[Reference1](https://github.com/edubart/minicoro), [Reference2](https://github.com/sysprog21/rv32emu/tree/master/tests/coro) | - | | 黃柏瑜 `^` | Optimize 2D line drawing for RV32IM using fixed-point arithmetic<br>[Reference](https://github.com/sysprog21/rv32emu/blob/master/tests/line.c) | [ Optimize 2D line drawing for RV32IM using fixed-point arithmetic](https://hackmd.io/@maromaSamsa/HkjefPbFs) | | 方宣翔 `^` | Implement RISC-V JIT compiler based on [xkon](https://github.com/ezaki-k/xkon_beta)<br>[Reference](https://hackmd.io/@oucs638/computer-arch-2021-fall-term-project) | [Implement RISC-V JIT compiler based on xkon](https://hackmd.io/zn1W2GPxRL6TiZS-3Ogcow) | | 1+ | Implement [Vector extension](https://github.com/riscv/riscv-v-spec) for [rv32emu](https://github.com/sysprog21/rv32emu) | - | | 1+ | Implement system emulation for [rv32emu](https://github.com/sysprog21/rv32emu) and boot Linux kernel<br>[Reference](https://gitlab.com/luplab/lupv) | - | | 陳彥甫 `^` | Reduce [rv32emu](https://github.com/sysprog21/rv32emu) instruction dispatch overhead<br>[Reference1](https://github.com/sysprog21/rv32emu/issues/88), [Reference](https://github.com/sysprog21/rv32emu/issues/81) | [Reduce rv32emu instruction dispatch overhead](https://hackmd.io/@qwe661234/S1XQAExti) | | 1+ | Make [rv32emu](https://github.com/sysprog21/rv32emu) fully compatible with RISC-V Architecture Tests, **RV32F** in particular<br>[Reference](https://github.com/sysprog21/rv32emu/issues/49) | - | | 1+ | Run [rv32emu](https://github.com/sysprog21/rv32emu) inside web browser via WebAssembly translation<br>[Reference](https://github.com/sysprog21/rv32emu/issues/75) | - | | 謝長成 `^` | Integrate embench-iot into [rv32emu](https://github.com/sysprog21/rv32emu) for benchmarking and compare with other ISS such as [Spike](https://github.com/riscv-software-src/riscv-isa-sim)<br>[Reference](https://github.com/sysprog21/rv32emu/issues/28) | [project](https://hackmd.io/@Osk-p534T9KkyTBAk79ijQ/Hyg1Y9gcj)| | 2 | Implement web-based RV32I emulator based on [riscv64-sim](https://github.com/iamlouk/riscv64-sim) | - | | 1+ | Make [WebRISC-V](https://github.com/Mariotti94/WebRISC-V) (web-based RISC-V pipeline simulator) compatibile with RISC-V Architecture Tests, **RV32I** and **RV32M** in particular.<br>[Reference](https://hackmd.io/@1llcMz45Qq2Mx4OlV8LHXQ/ryRo_ulnY) | - | | 2 | Implement Linux userspace RV32 emulation for [RVVM](https://hackmd.io/@huang-me/ca_rvvm)<br>[Reference](https://hackmd.io/@huang-me/ca_rvvm) | - | | 1+ | Improve RV32I coverage for [emulsiV](https://github.com/ESEO-Tech/emulsiV) (Web-based RISC-V simulator) | - | | 張瑞甫 `^` | Build a RV32I compatible processor core and SoC<br>[Reference](https://hackmd.io/@w4K9apQGS8-NFtsnFXutfg/B1Re5uGa5) | [chiwawa&peipeibeast](https://hackmd.io/@CWWPPB/S1HVmuvuo) | |1+ | Study [tinygpus](https://github.com/sylefeb/tinygpus) (Make your own graphics hardware!) | - | | 莊集 <br>吳峻廷 | Study [XGSoC](https://github.com/dcliche/xgsoc) (FPGA based system on chip with audio, video and 3D acceleration) and ensure simulation functionality by integrating more samples | [XGSoC](https://hackmd.io/Vo0cJDOBTHaw8YfU9kzkmw?view) | | 1+ | Study [Minimax](https://github.com/gsmecher/minimax) (Compressed-First, Microcoded RISC-V core). Use FuseSOC for somulation.<br>[Reference](https://news.ycombinator.com/item?id=33422717) | - | | 1+ | Study [Vicuna](https://github.com/vproc/vicuna) (RISC-V Zve32x Vector Coprocessor) and simulate properly. | - | | 1+ | Integrate [RISC-V Unit Tests](https://github.com/riscv-software-src/riscv-tests) for [LupV](https://gitlab.com/luplab/lupv) and consolidate its complaince | - | | 1 | Accelerate [LupV](https://gitlab.com/luplab/lupv) system emulation with the techniques used in [rv32emu](https://github.com/sysprog21/rv32emu) | - | | 1+ | Study [riscv-mini](https://github.com/ucb-bar/riscv-mini) (Simple RISC-V 3-stage Pipeline) and upgrade to Latest RISC-V Spec<br>[Reference](https://github.com/ucb-bar/riscv-mini/pull/49) | - | | 1+ | Implement MMU for [mini-rv32ima](https://github.com/cnlohr/mini-rv32ima) to boot xv6 or Linux<br>[Reference1](https://github.com/jserv/semu), [Reference2](https://github.com/qqgnoe466263/rv32-emu), [Reference3](https://youtu.be/YT5vB3UqU_E) | - | | 陳奕萍 `^` | Study [PicoRV32](https://github.com/YosysHQ/picorv32) and [add custom instructions](https://github.com/uki-a/custom-riscv) which can be recognized/manipulated by the processor<br>[Reference](https://hackmd.io/@30vhEV7FQECcWeCF1eAN5A/S1ybboVnK) | [PicoRV32](https://hackmd.io/@P76111482/HJ6r7CHcj) | | 陳柏瑋 | Implement RV32M for [spu32](https://github.com/maikmerten/spu32) (compact RV32I core)<br>[Reference](https://hackmd.io/@509/rkRZt-NnY) | [Analysis RV32M for spu32](https://hackmd.io/@JxPCbLVmQh2_5-6E4fvX9w/Sya7aCi9s) | | 馮柏為 陳品崴 周士翔 | Cache simulation and case study<br>[Reference](https://hackmd.io/@AOmdVHgtTeW-V72uCBTjTw/rkfoi17Tt) | [Cache simulation and case study](https://hackmd.io/@r1YLxwFRRPe1xninh0Ma6w/SJRrVgQcj) | | 黃冠予 俞杉麒 王昱承 `^` | RISC-V Cache implementation and software optimization case study<br>[Reference](https://hackmd.io/@_UHs74UQS7uNne9_7SwQFQ/HyFHdpw3t) | [RISC-V Cache implementation and software optimization case study](https://hackmd.io/@zKOCm3SSTKyUyiPV-nfEjw/ByyIBzzuo/edit) | | 1 | Optimize [QR code generation](https://www.nayuki.io/page/creating-a-qr-code-step-by-step) programs (tweaked for [srv32](https://github.com/kuopinghsu/srv32), RV32IM)<br>[Reference1](https://github.com/sysprog21/rv32emu/blob/master/tests/qrcode.c), [Reference](https://github.com/fabiankuffer/RISC-V-QR-Code-Generator) | - | | 潘鴻福 `^` | Implement RISCV pipelined processor from scratch<br>[Reference](https://github.com/Ellllipse/RISCV-processor-design) | [Build RISC-V pipelined processor from scratch](https://hackmd.io/@kaminto-1999/final-project)| | 鄒崴丞 王漢祺 `^` | Study [RISCV-Atom](https://github.com/saursin/riscv-atom) (32-bit embedded-class RISC-V processor) and implement RV32M | [RISCV-Atom and implement RV32M](https://hackmd.io/@wanghanchi/SJTRpltqj) | | 陳靖雯 `^` | RV32 port for latest [MIT xv6 operating system](https://github.com/mit-pdos/xv6-riscv) (and contribute!)<br>[Rerefence1](https://www.uni-bamberg.de/fileadmin/sysnap/slides/xv6-riscv.pdf), [Reference2](https://github.com/harihitode/ladybird-xv6), [Reference3](https://ithelp.ithome.com.tw/m/users/20138181/ironman/5395), [Reference4](https://www.youtube.com/user/hhp3/videos) | [RV32 port for latest MIT xv6 operating system](https://hackmd.io/@ihvNzfsUS1GqCZHdnD-iWw/HJu_RZs5j) | | 張邦翰 `^` | Study [FRISCV](https://github.com/dpretet/friscv) (SystemVerilog implementation of RISC-V) | [FRISCV Analysis](https://hackmd.io/@fycuo5VWT7KIkq5eWMwXag/friscv) | | 1+ | Study [Ladybird](https://github.com/harihitode/ladybird) and analyze how xv6 runs | - | | 賴致文 `^` | Analyze [CKB VM AOT](https://github.com/mohanson/ckb-vm-aot), high performance RISC-V runtime written in Rust | [Analyze ckb-vm-aot](https://hackmd.io/@b3nzYEHmSeCBZhvZgxI-DA/H1Wnj4bcs) |
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