Computer Archiecture 2022: Term Project

You must provide the materials and demonstrate to the lecturer before Jan 13, 2023

Fill in the table for your term project

• Send email to <[e-mail]> to confirm the details and expectations.
• Numbers denote the expected sizes of the teams, and you should replace them with your name(s) if you are about to take the task.
• New items MUST NOT be added. Instead, you should just provide your name(s) and any relevant hyperlinks to your progress.
• Be aware of spaces while editing.
• Reference: Terms projects for 2021

Group (add your name here)	Topic	Your Hyperlinks
1	Implement A (atomic) extension for srv32MIT and verify with FreeRTOS Reference	-
張中龍 吳紀寬 ^	Implement dynamic/static branch prediction for srv32MIT Reference	Implement dynamic/static branch prediction for srv32
江坤諦 ^	Run FreeRTOS on VexRiscv and Meature/Tweak context switch overhread Reference	Run FreeRTOS on VexRiscv and Meature/Tweak context switch overhread
陳韋勳 ^	Annotate and explain Quiz4/Quiz5 with Ripes simulation Reference	Quiz4 / Quiz5
吳宇晨 ^	Rework Homework1	rework HW1
何坤霖 ^	Rework Homework3 (variant-A)	Rework HW3
黃昱澄 ^	Rework Homework3 (variant-B)	rework HW3
楊淳皓 ^	Rework Homework3 (variant-C)	Rework HW3
鄭明奇 ^	Enable sounds for Quake video game on rv32emuMIT by implementing new system calls Reference	Project : add sound of quake on rv32emu
曾晧峖 ^	Reduce memory usage for Doom running on rv32emu Reference1, Reference2	Reduce memory usage for DOOM
2+	Analyze minrv32 and Consolidate RV32I/M/C (should be compliant with riscv-tests). Reference: 2021, 2022	-
2+	Contribute to Ripes: pick up pending issues, work on them, and finally send pull request(s) for reviewing. Reference	-
洪嘉志 ^	Validate the pipeline design of kleine-riscv and Implement RV32M Reference	Validate the pipeline design of kleine-riscv and Implement RV32M
鄭至崴 ^	Analyze femtorv-quark and ensure RV32I compatibility Reference1, Reference2	Analyze femtorv-quark and ensure RV32I compatibility
黃榆哲 蘇勇達 ^	Port FreeRTOS on femtorv and prepare showcase Reference	Port FreeRTOS on femtorv and prepare showcase
2+	Contribute to NEORV32 (MCU-class 32-bit RISC-V soft-core CPU) Reference	-
1	Contribute RV32 support for Tina (header only, coroutine and fiber library) Reference1, Reference2	-
黃柏瑜 ^	Optimize 2D line drawing for RV32IM using fixed-point arithmetic Reference	Optimize 2D line drawing for RV32IM using fixed-point arithmetic
方宣翔 ^	Implement RISC-V JIT compiler based on xkon Reference	Implement RISC-V JIT compiler based on xkon
1+	Implement Vector extension for rv32emu	-
1+	Implement system emulation for rv32emu and boot Linux kernel Reference	-
陳彥甫 ^	Reduce rv32emu instruction dispatch overhead Reference1, Reference	Reduce rv32emu instruction dispatch overhead
1+	Make rv32emu fully compatible with RISC-V Architecture Tests, RV32F in particular Reference	-
1+	Run rv32emu inside web browser via WebAssembly translation Reference	-
謝長成 ^	Integrate embench-iot into rv32emu for benchmarking and compare with other ISS such as Spike Reference	project
2	Implement web-based RV32I emulator based on riscv64-sim	-
1+	Make WebRISC-V (web-based RISC-V pipeline simulator) compatibile with RISC-V Architecture Tests, RV32I and RV32M in particular. Reference	-
2	Implement Linux userspace RV32 emulation for RVVM Reference	-
1+	Improve RV32I coverage for emulsiV (Web-based RISC-V simulator)	-
張瑞甫 ^	Build a RV32I compatible processor core and SoC Reference	chiwawa&peipeibeast
1+	Study tinygpus (Make your own graphics hardware!)	-
莊集 吳峻廷	Study XGSoC (FPGA based system on chip with audio, video and 3D acceleration) and ensure simulation functionality by integrating more samples	XGSoC
1+	Study Minimax (Compressed-First, Microcoded RISC-V core). Use FuseSOC for somulation. Reference	-
1+	Study Vicuna (RISC-V Zve32x Vector Coprocessor) and simulate properly.	-
1+	Integrate RISC-V Unit Tests for LupV and consolidate its complaince	-
1	Accelerate LupV system emulation with the techniques used in rv32emu	-
1+	Study riscv-mini (Simple RISC-V 3-stage Pipeline) and upgrade to Latest RISC-V Spec Reference	-
1+	Implement MMU for mini-rv32ima to boot xv6 or Linux Reference1, Reference2, Reference3	-
陳奕萍 ^	Study PicoRV32 and add custom instructions which can be recognized/manipulated by the processor Reference	PicoRV32
陳柏瑋	Implement RV32M for spu32 (compact RV32I core) Reference	Analysis RV32M for spu32
馮柏為 陳品崴 周士翔	Cache simulation and case study Reference	Cache simulation and case study
黃冠予 俞杉麒 王昱承 ^	RISC-V Cache implementation and software optimization case study Reference	RISC-V Cache implementation and software optimization case study
1	Optimize QR code generation programs (tweaked for srv32, RV32IM) Reference1, Reference	-
潘鴻福 ^	Implement RISCV pipelined processor from scratch Reference	Build RISC-V pipelined processor from scratch
鄒崴丞 王漢祺 ^	Study RISCV-Atom (32-bit embedded-class RISC-V processor) and implement RV32M	RISCV-Atom and implement RV32M
陳靖雯 ^	RV32 port for latest MIT xv6 operating system (and contribute!) Rerefence1, Reference2, Reference3, Reference4	RV32 port for latest MIT xv6 operating system
張邦翰 ^	Study FRISCV (SystemVerilog implementation of RISC-V)	FRISCV Analysis
1+	Study Ladybird and analyze how xv6 runs	-
賴致文 ^	Analyze CKB VM AOT, high performance RISC-V runtime written in Rust	Analyze ckb-vm-aot