# FRISCV Analysis
###### tags: `RISC-V` `Verilator` `iVerilog` `SVUT` `FreeRTOS`
> ai-creator-lab 2023
:::info
:bulb: **Note**: The goal of this research is to explore the [FRISCV Repo](https://github.com/dpretet/friscv.git)
* Introduction
* Prerequisites
* Architecture
* CLINT
* Limitations of CLINT
* FreeRTOS Overview
* Running FreeRTOS on FRISCV
* Exploring Cache Behavior of FRISCV
* Conclusion
:::
### Introduction
FRISCV is a 3-stage in-order pipelined soft CPU written in SystemVerilog, supporting RV32I/RV32E, and M extension. In terms of priviledge model, only M mode is supported. Additionally, the CLINT extension was implemented.
### Prerequisites
```bash=
$ pacman -Syu verilator iverilog cmake python gcc
$ pip install svut
$ git clone --recursive https://github.com/dpretet/friscv.git
Submodule 'dep/axi-crossbar' (https://github.com/dpretet/axi-crossbar.git) registered for path 'dep/axi-crossbar'
Submodule 'dep/svlogger' (https://github.com/dpretet/svlogger.git) registered for path 'dep/svlogger'
Submodule path 'dep/axi-crossbar': checked out '7738a3811623ef4b5610082347bfecce35d95dd2'
Submodule 'deps/dcfifo' (https://github.com/dpretet/async_fifo.git) registered for path 'dep/axi-crossbar/deps/dcfifo'
Submodule 'deps/svlogger' (https://github.com/dpretet/svlogger.git) registered for path 'dep/axi-crossbar/deps/svlogger'
Submodule path 'dep/axi-crossbar/deps/dcfifo': checked out '2c7560a84bee1026a17828fad5788a8f7014bfd3'
Submodule path 'dep/axi-crossbar/deps/svlogger': checked out '410edf2f694462cc40061d535d8a90bc4cbfcb30'
Submodule path 'dep/svlogger': checked out '1e1f22b4da5c4cb580f163fc6611566590015ee5'
$ git clone --recursive https://github.com/FreeRTOS/FreeRTOS-Kernel.git
Submodule 'ThirdParty/FreeRTOS-Kernel-Community-Supported-Ports' (https://github.com/FreeRTOS/FreeRTOS-Kernel-Community-Supported-Ports) registered for path 'portable/ThirdParty/Community-Supported-Ports'
Submodule 'ThirdParty/FreeRTOS-Kernel-Partner-Supported-Ports' (https://github.com/FreeRTOS/FreeRTOS-Kernel-Partner-Supported-Ports) registered for path 'portable/ThirdParty/Partner-Supported-Ports'
Kernel/portable/ThirdParty/Partner-Supported-Ports'...
Submodule path 'portable/ThirdParty/Community-Supported-Ports': checked out '4273ca3211b99914f31518378fb590fbff064953'
Submodule path 'portable/ThirdParty/Partner-Supported-Ports': checked out '3f9c99a682c5c796bb7eb89fd9c4385688fce27a'
```
#### Explanation
Verilator and iVerilog are neccessary for Systemverilog simulation.
SVUT is SystemVerilog Unit Test, a Python package written by the author of FRISCV, the workflow of whole project heavily depends on this.
As of 2023/01/13, Verilator is not fully supported in FRISCV/SVUT, so you need iVerilog
:::warning
:bulb: **If you are using an outdated distribution like Ubuntu, you will need to compile Verilator and iVerilog from source to get on a decent version, FRISCV depends on this.**
**For reference the following versions I have tested to be working with the test suite of FRISCV are mentioned:**
> Verilator(5.004)
> iVerilog(12.0)
:::
### Architecture
:::info
:bulb: **Note**: The original repo already have good explanation on most things, will not repeat everything, only the most relevant bits will be presented here
:::
Core Level
[]
Platform Level
#### Explanation:
The core itself is not all that useful, so FRISCV uses the AXI4-lite Crossbar to connect signals and modules like CLINT, UART, GPIOs. In terms of code, this means that there are two levels of top_module that you can use. Notably, there is also a JTAG interface for debugging.
#### TLDR:
use the Core or Platform as top_module according to your needs.
**Interrupts**
RIC-V interrupts are named according to their priviledge mode, and each HART is under a certain mode. For example, mtime's m stand for M mode. Software and hardware interupts
The implemented interupts are **MEIP**, **MTIP**, **MSIP(i/o)**.
**MEIP** is for receiving external input. While **MTIP** and **MSIP** are implemented on the CLINT(explained in the next section)
### CLINT
**CLINT** is the **Core Local Interrupt Controller** which is a small external module connected to the core. CLINT provides **machine level IPI(Inter-Processor Interupt)** and **local timer** functionalities.Next, we explain the interrupts implemented in FRISCV's CLINT **MTIP** enables generating timer interrupts for each core. **MSIP(i/o)** enables software interrupts from other **HARTs** input/output.
### Limitations of CLINT
:::info
:bulb: **Note**: Since FRISCV only implements M mode, the following explanation on limitations of **CLINT** will be concise.
:::
**CLINT only operates under M mode**, other priviledge modes
must use **mideleg**. Also, CLINT has a unified register map for both IPI and timer, this is a limitation and unnecessary coupling, so new RISC-V specifications are currently under draft to decouple the above and provide support for **IPI under S mode**
### FreeRTOS Overview
**FreeRTOS** stands for Free Real Time Operating System. Real-Time Systems demand that the scheduling of different tasks to meet different deadlines, this means that behavior should be predictable. Real-time Tasks can be defined as hard or soft real-time, hard means that missing the deadline is fatal(think life-critical systems like ABS on vehicles), while soft is mostly a best effort basis(think rendering).
While the Linux kernel has a maintained set of patches called **PREEMPT_RT**, which is neccessary since having the most performance often means that the system is unpredictable(think migration) and thus, might miss deadlines, it is still an ongoing effort towards hard real-time. Moreover the ability of the underlying hardware, interrupt latency and the scheduler and its parameters also contributes to hard real-time capabilities. Modern industrial control applications still run on resource-constrained devices, where the Linux Kernel does not fit. This is where FreeRTOS shines, as it takes a lot less resource to run on the target device.
:::info
:bulb: **Note that there is an ongoing effort to merge PREMPT_RT into mainline Linux Kernel. This has not been completed yet as of 2023/01/13, and will likely take quite some time, as some patches touches code in the mainline that otherwise seems fine**
:::
#### Architecture of FreeRTOS
FreeRTOS can be viewed as several layers stacked upon each other, hardware dependent code stacked on bare metal, hardware independent code stack in the middle, while user tasks and interrupt service routines(ISR) are on the top. Being a RTOS for a wide variety of ISAs and compilers, in order to suit different needs of users, FreeRTOS is highly configurable. The configurations of FreeRTOS is specified by using the #define directive in **FreeRTOSConfig.h**, thus it is possible to have a wide range of configurations, from running tasks on resource-constrained devices to running full blown SMP, Network/Peripheral stack. This is especially important for architectures like RISC-V
:::info
**Since RISC-V chip implementations often include chip-specific extensions, you must set the appropriate configurations for FreeRTOS to take full advantage of the chip.**
**For FRISCV config the followings:**
```clike=
#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
#define __FREERTOS_RISC_V_EXTENSIONS_H__
#define portasmHAS_SIFIVE_CLINT 1
#define portasmHAS_MTIME 1
#define portasmADDITIONAL_CONTEXT_SIZE 0
#endif
```
#### Explanations
Line 1 means that we are using RISC-V extensions
Line 4 enables CLINT support because FRISCV implemented this
Line 5 enables MTIME this CSR is implemented in FRISCV
Line 6 is set to 0 since we don't have additonal registers not mandated by the spec
:::
### Status
:::danger
:bulb:As of now, this is not yet completed, partially due to the script in the repo not doing what its supposed to and that I haven't figured out SVUT yet. To be updated.
:::
### Running FreeRTOS on FRISCV
### Exploring Cache Behavior of FRISCV
### Conclusion
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