# Term Project: Rework Homework3 (variant-C)
###### tags: `Computer Architecture` `RISC-V` `jserv`
> Contributed by <[tonych1997](https://github.com/tonych1997/Computer-Architecture)>
[Computer Archiecture 2022: Term Project](https://hackmd.io/@sysprog/arch2022-projects)
[Assignment3 Requirements](https://hackmd.io/@sysprog/2022-arch-homework3)
[Lab3: srv32 - RISCV RV32IM Soft CPU](https://hackmd.io/@sysprog/S1Udn1Xtt)
[Github - srv32](https://github.com/sysprog21/srv32)
[Compliance Test in srv32](https://github.com/kuopinghsu/srv32/tree/master/tests)
## Set up the enviroment
### [Set enviroment variables](https://hackmd.io/pohwp5E8SNeuTo66J-2-pw?both#Set-up-the-enviroment)
Base on my [hw3](https://hackmd.io/@Vgwl_uixQFasIvsDbsFlvA/risc-v-hw3)'s enviroment. These steps need to be done first at the beginning of each session.
Confirm the Environment Variables and PATH settings.
```
$ export # Check PATH, CROSS_COMPILE, VERILATOR_ROOT etc.
$ echo $PATH # check PATH only
```
Shutting down, rebooting, turning off the terminal, restarting the terminal, using a different terminal, etc. can cause the Environment Variables or PATH to be lost.
If the Environment Variable is missing, run the following command to reset the it.
```
# Set Cross Compile and Verilator root
$ export CROSS_COMPILE=riscv-none-elf-
$ export VERILATOR_ROOT=$HOME/verilator
```
If the PATH is missing, run the following command to reset it.
```
# Set RISC-V toolchain PATH
$ cd $HOME/riscv-none-elf-gcc
$ echo "export PATH=`pwd`/bin:$PATH" > setenv
$ cd $HOME
$ source riscv-none-elf-gcc/setenv
```
```
# Set verilator PATH
$ export PATH=$VERILATOR_ROOT/bin:$PATH
```
### Set Compliance Test
First I refer to the [github](https://github.com/kuopinghsu/srv32/tree/master/tests) mentioned in the letter and refer to the installation approach there.
```
export ROOT_SRV32=<root path of simple RISCV>
cp -r ${ROOT_SRV32}/tests/srv32 <path of riscv-arch-test>/riscv-target/.
cd ${ROOT_SRV32}
make build
export CROSS_COMPILE=riscv64-unknown-elf-
export TARGET_SIM=${ROOT_SRV32}/sim/sim
export RISCV_PREFIX=${CROSS_COMPILE}
export RISCV_TARGET=srv32
make
export TARGET_SIM=${ROOT_SRV32}/tools/rvsim
export RISCV_PREFIX=${CROSS_COMPILE}
export RISCV_TARGET=srv32
make
```
Then I noticed that some steps needed to be modified.
Set `ROOT_SRV32` path.
```
$ export ROOT_SRV32=/home/t123/srv32
```
In the directory `tests` have two `srv32`, one is `srv32.v1`, and another one is `srv32.v2`.
I observe the files in the `srv32.v1` and `srv32.v2` paths, respectively, as follows.
The file under `srv32.v1` is shown in the following figure.
The file under `srv32.v2` is shown in the following figure.
I discoverd there is no `srv32` in the dircetory `tests`, but `srv32` is already in directory `path of riscv-arch-test>/riscv-target/.`.
In the termianl, I can see these contents in `../riscv-target/` directory.
However, I also found that the files under the `srv32/tests/riscv-arch-tests.v2/` path and the files in `riscv-non-isa/riscv-arch-tests/old-framework-2.x/` have the same contents, but are different from the files in `riscv-non-isa/riscv-arch-test/main`.
In `main` branch, the files as shown as follow.
In `old-framework-2.x` branch, the files as shown as follow.
Therefore, **I did not do above step**.
```
# Original command
$ cp -r ${ROOT_SRV32}/tests/srv32 <path of riscv-arch-test>/riscv-target/.
# My Command
$ cp -r ${ROOT_SRV32}/tests/srv32.v2 /home/t123/srv32/tests/riscv-arch-test.v2/riscv-target/.
```
The next step is to set up `CROSS_COMPILE`, which has been set up before and differs from the document, as shown below.
```
$ export CROSS_COMPILE=riscv-none-elf-
```
## Requirement 1
**Automate the verification of the Homework3 code and run it on srv32.**
According to the [kuopinghsu/srv32 Github](https://github.com/kuopinghsu/srv32)'s [RTL command](https://github.com/kuopinghsu/srv32#rtl-simulation), I see that using the `make tests-all` command can run all diags and compliance test, and `make test_v=2 tests-all ` can run all tests with test compliance v2.
So I changed the command to the following one to run all tests with test compliance v2 on the specified file.
```
# run "filename" tests with test compliance v2
$ make test_v=2 tests filename
```
### Q1: Assignement 2 - Search Insert Position
Search Insert Position v2 code is [here](https://hackmd.io/LJeLMHbrRnqaLhL7LCQNkw?view#Software-Optimizations).
Then I do a compliance test on this program.
```
$ make test_v=2 tests sip2
```
:::spoiler result
```
make coverage=0 clean && make rv32c=0 memsize=1716 -C sim; make rv32c=0 -C tools
make[1]: Entering directory '/home/t123/srv32'
for i in sw sim tools tests coverage; do \
make test_v=2 -C $i clean; \
done
make[2]: Entering directory '/home/t123/srv32/sw'
for i in pi_pthread perf irq hello pi sip2 sip qsort sem coremark 122 dhrystone common; do \
if [ -f $i/Makefile ]; then \
make -C $i clean; \
fi; \
done
make[3]: Entering directory '/home/t123/srv32/sw/pi_pthread'
rm -f *.o pi_pthread.dis pi_pthread.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/pi_pthread'
make[3]: Entering directory '/home/t123/srv32/sw/perf'
rm -f *.o perf.dis perf.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/perf'
make[3]: Entering directory '/home/t123/srv32/sw/irq'
rm -f *.o irq.elf irq.dis irq.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/irq'
make[3]: Entering directory '/home/t123/srv32/sw/hello'
rm -f *.o hello.elf hello.dis hello.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/hello'
make[3]: Entering directory '/home/t123/srv32/sw/pi'
rm -f *.o pi.elf pi.dis pi.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/pi'
make[3]: Entering directory '/home/t123/srv32/sw/sip2'
rm -f *.o sip2.elf sip2.dis sip2.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/sip2'
make[3]: Entering directory '/home/t123/srv32/sw/sip'
rm -f *.o sip.elf sip.dis sip.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/sip'
make[3]: Entering directory '/home/t123/srv32/sw/qsort'
rm -f *.o qsort.elf qsort.dis qsort.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/qsort'
make[3]: Entering directory '/home/t123/srv32/sw/sem'
rm -f *.o sem.dis sem.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/sem'
make[3]: Entering directory '/home/t123/srv32/sw/coremark'
rm -f ./coremark.elf ./*.log *.info ./index.html
rm -f coremark.dis coremark.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/coremark'
make[3]: Entering directory '/home/t123/srv32/sw/122'
rm -f *.o 122.elf 122.dis 122.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/122'
make[3]: Entering directory '/home/t123/srv32/sw/dhrystone'
rm -f *.o dhrystone.elf dhrystone.dis dhrystone.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/dhrystone'
make[3]: Entering directory '/home/t123/srv32/sw/common'
rm -f startup.o syscall.o libsys.a
make[3]: Leaving directory '/home/t123/srv32/sw/common'
make[2]: Leaving directory '/home/t123/srv32/sw'
make[2]: Entering directory '/home/t123/srv32/sim'
make[2]: Leaving directory '/home/t123/srv32/sim'
make[2]: Entering directory '/home/t123/srv32/tools'
rm -f rvsim.o decompress.o syscall.o elfread.o getch.o dump.txt trace.log trace.log.dis rvsim out.bin
if [ 0 = 0 ]; then \
rm -f -rf html coverage.info *.gcda *.gcno *.gcov; \
fi
make[2]: Leaving directory '/home/t123/srv32/tools'
make[2]: Entering directory '/home/t123/srv32/tests'
rm -rf riscv-arch-test.v2/work
make[2]: Leaving directory '/home/t123/srv32/tests'
make[2]: Entering directory '/home/t123/srv32/coverage'
make[2]: Leaving directory '/home/t123/srv32/coverage'
make[1]: Leaving directory '/home/t123/srv32'
make[1]: Entering directory '/home/t123/srv32/sim'
verilator -O3 -cc -Wall -Wno-STMTDLY -Wno-UNUSED +define+MEMSIZE=1716 --trace-fst --Mdir sim_cc --build --exe sim_main.cpp getch.cpp -o sim -f filelist.txt ../rtl/top.v
make[2]: Entering directory '/home/t123/srv32/sim/sim_cc'
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o getch.o ../getch.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o sim_main.o ../sim_main.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o verilated.o /home/t123/verilator/include/verilated.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o verilated_dpi.o /home/t123/verilator/include/verilated_dpi.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o verilated_fst_c.o /home/t123/verilator/include/verilated_fst_c.cpp
/usr/bin/perl /home/t123/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vriscv.cpp Vriscv___024root__DepSet_ha08c5775__0.cpp Vriscv___024root__DepSet_h309ef4e5__0.cpp Vriscv___024unit__DepSet_h6996a1c2__0.cpp Vriscv__Dpi.cpp Vriscv__Trace__0.cpp Vriscv__ConstPool_0.cpp Vriscv___024root__Slow.cpp Vriscv___024root__DepSet_ha08c5775__0__Slow.cpp Vriscv___024root__DepSet_h309ef4e5__0__Slow.cpp Vriscv___024unit__Slow.cpp Vriscv___024unit__DepSet_h69b9c73c__0__Slow.cpp Vriscv__Syms.cpp Vriscv__Trace__0__Slow.cpp > Vriscv__ALL.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o Vriscv__ALL.o Vriscv__ALL.cpp
echo "" > Vriscv__ALL.verilator_deplist.tmp
Archive ar -rcs Vriscv__ALL.a Vriscv__ALL.o
g++ getch.o sim_main.o verilated.o verilated_dpi.o verilated_fst_c.o Vriscv__ALL.a -lz -o sim
rm Vriscv__ALL.verilator_deplist.tmp
make[2]: Leaving directory '/home/t123/srv32/sim/sim_cc'
mv sim_cc/sim .
make[1]: Leaving directory '/home/t123/srv32/sim'
make[1]: Entering directory '/home/t123/srv32/tools'
gcc -c -o rvsim.o rvsim.c -O3 -g -Wall
gcc -c -o decompress.o decompress.c -O3 -g -Wall
gcc -c -o syscall.o syscall.c -O3 -g -Wall
gcc -c -o elfread.o elfread.c -O3 -g -Wall
gcc -c -o getch.o getch.c -O3 -g -Wall
gcc -O3 -g -Wall -o rvsim rvsim.o decompress.o syscall.o elfread.o getch.o
make[1]: Leaving directory '/home/t123/srv32/tools'
make memsize=1716 test_v=2 rv32c=0 -C tests tests
make[1]: Entering directory '/home/t123/srv32/tests'
if [ "2" = "1" ]; then \
if [ ! -d riscv-arch-test.v1 ]; then \
git clone -b 1.0 https://github.com/riscv/riscv-arch-test.git riscv-arch-test.v1; \
fi; \
rm -rf riscv-arch-test.v1/riscv-target/srv32; \
cp -r srv32.v1 riscv-arch-test.v1/riscv-target/srv32; \
else \
if [ ! -d riscv-arch-test.v2 ]; then \
git clone -b 2.7.4 https://github.com/riscv/riscv-arch-test.git riscv-arch-test.v2; \
fi; \
echo; \
rm -rf riscv-arch-test.v2/riscv-target/srv32; \
cp -r srv32.v2 riscv-arch-test.v2/riscv-target/srv32; \
fi
export ROOT_SRV32=/home/t123/srv32; \
export TARGET_SIM="/home/t123/srv32/sim/sim +trace"; \
export TARGET_SWSIM="/home/t123/srv32/tools/rvsim --memsize 1716"; \
export RISCV_PREFIX=riscv-none-elf-; \
export RISCV_TARGET=srv32; \
make rv32c=0 -C riscv-arch-test.v2
make[2]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2'
============================ VARIABLE INFO ==================================
ROOTDIR: /home/t123/srv32/tests/riscv-arch-test.v2 [origin: file]
WORK: /home/t123/srv32/tests/riscv-arch-test.v2/work [origin: file]
TARGETDIR: /home/t123/srv32/tests/riscv-arch-test.v2/riscv-target [origin: file]
RISCV_TARGET: srv32 [origin: environment]
XLEN: 32 [origin: file]
RISCV_DEVICE: I [origin: file]
=============================================================================
make[3]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2'
============================ VARIABLE INFO ==================================
ROOTDIR: /home/t123/srv32/tests/riscv-arch-test.v2 [origin: file]
WORK: /home/t123/srv32/tests/riscv-arch-test.v2/work [origin: environment]
TARGETDIR: /home/t123/srv32/tests/riscv-arch-test.v2/riscv-target [origin: environment]
RISCV_TARGET: srv32 [origin: command line]
XLEN: 32 [origin: environment]
RISCV_DEVICE: I [origin: command line]
=============================================================================
make -j1 \
RISCV_TARGET=srv32 \
RISCV_DEVICE=I \
run -C /home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/I
make[4]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/I'
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/add-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/add-01.log
Excuting 3242 instructions, 3248 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.139 s
Simulation cycles: 3259
Simulation speed : 0.023446 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/addi-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/addi-01.log
Excuting 2170 instructions, 2176 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.132 s
Simulation cycles: 2187
Simulation speed : 0.0165682 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/and-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/and-01.log
Excuting 3218 instructions, 3224 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.165 s
Simulation cycles: 3235
Simulation speed : 0.0196061 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/andi-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/andi-01.log
Excuting 2170 instructions, 2176 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.145 s
Simulation cycles: 2187
Simulation speed : 0.0150828 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/auipc-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/auipc-01.log
Excuting 422 instructions, 428 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.139 s
Simulation cycles: 439
Simulation speed : 0.00315827 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/beq-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/beq-01.log
Excuting 5546 instructions, 7934 cycles, 1.430 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.139 s
Simulation cycles: 7945
Simulation speed : 0.0571583 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bge-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bge-01.log
Excuting 5596 instructions, 8576 cycles, 1.532 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.131 s
Simulation cycles: 8587
Simulation speed : 0.0655496 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bgeu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bgeu-01.log
Excuting 6838 instructions, 10500 cycles, 1.535 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.13 s
Simulation cycles: 10511
Simulation speed : 0.0808538 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/blt-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/blt-01.log
Excuting 5511 instructions, 8385 cycles, 1.521 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.138 s
Simulation cycles: 8396
Simulation speed : 0.0608406 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bltu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bltu-01.log
Excuting 6830 instructions, 10444 cycles, 1.529 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.151 s
Simulation cycles: 10455
Simulation speed : 0.0692384 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bne-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bne-01.log
Excuting 5549 instructions, 9011 cycles, 1.623 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.156 s
Simulation cycles: 9022
Simulation speed : 0.0578333 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jal-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jal-01.log
Excuting 520 instructions, 722 cycles, 1.388 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.112 s
Simulation cycles: 733
Simulation speed : 0.00654464 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jalr-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jalr-01.log
Excuting 498 instructions, 636 cycles, 1.277 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.14 s
Simulation cycles: 647
Simulation speed : 0.00462143 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lb-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lb-align-01.log
Excuting 298 instructions, 304 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 315
Simulation speed : 0.00244186 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lbu-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lbu-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.132 s
Simulation cycles: 311
Simulation speed : 0.00235606 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lh-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lh-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 311
Simulation speed : 0.00241085 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lhu-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lhu-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.138 s
Simulation cycles: 311
Simulation speed : 0.00225362 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lui-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lui-01.log
Excuting 226 instructions, 232 cycles, 1.026 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.128 s
Simulation cycles: 243
Simulation speed : 0.00189844 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lw-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lw-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.128 s
Simulation cycles: 311
Simulation speed : 0.00242969 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/or-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/or-01.log
Excuting 3242 instructions, 3248 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.145 s
Simulation cycles: 3259
Simulation speed : 0.0224759 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/ori-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/ori-01.log
Excuting 2166 instructions, 2172 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.133 s
Simulation cycles: 2183
Simulation speed : 0.0164135 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sb-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sb-align-01.log
Excuting 618 instructions, 624 cycles, 1.009 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.126 s
Simulation cycles: 635
Simulation speed : 0.00503968 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sh-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sh-align-01.log
Excuting 622 instructions, 628 cycles, 1.009 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.138 s
Simulation cycles: 639
Simulation speed : 0.00463044 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sll-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sll-01.log
Excuting 498 instructions, 504 cycles, 1.012 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.127 s
Simulation cycles: 515
Simulation speed : 0.00405512 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slli-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slli-01.log
Excuting 402 instructions, 408 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 419
Simulation speed : 0.00324806 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slt-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slt-01.log
Excuting 3222 instructions, 3228 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.14 s
Simulation cycles: 3239
Simulation speed : 0.0231357 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slti-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slti-01.log
Excuting 2166 instructions, 2172 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.144 s
Simulation cycles: 2183
Simulation speed : 0.0151597 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltiu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltiu-01.log
Excuting 2650 instructions, 2656 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.152 s
Simulation cycles: 2667
Simulation speed : 0.0175461 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltu-01.log
Excuting 3910 instructions, 3916 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.157 s
Simulation cycles: 3927
Simulation speed : 0.0250127 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sra-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sra-01.log
Excuting 502 instructions, 508 cycles, 1.011 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.13 s
Simulation cycles: 519
Simulation speed : 0.00399231 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srai-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srai-01.log
Excuting 402 instructions, 408 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.134 s
Simulation cycles: 419
Simulation speed : 0.00312687 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srl-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srl-01.log
Excuting 514 instructions, 520 cycles, 1.011 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.124 s
Simulation cycles: 531
Simulation speed : 0.00428226 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srli-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srli-01.log
Excuting 410 instructions, 416 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.14 s
Simulation cycles: 427
Simulation speed : 0.00305 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sub-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sub-01.log
Excuting 3262 instructions, 3268 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.135 s
Simulation cycles: 3279
Simulation speed : 0.0242889 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sw-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sw-align-01.log
Excuting 602 instructions, 608 cycles, 1.009 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.126 s
Simulation cycles: 619
Simulation speed : 0.0049127 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xor-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xor-01.log
Excuting 3238 instructions, 3244 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.13 s
Simulation cycles: 3255
Simulation speed : 0.0250385 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xori-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xori-01.log
Excuting 2186 instructions, 2192 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.138 s
Simulation cycles: 2203
Simulation speed : 0.0159638 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/fence-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/fence-01.log
Excuting 106 instructions, 112 cycles, 1.056 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.157 s
Simulation cycles: 123
Simulation speed : 0.000783439 MHz
make[4]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/I'
riscv-test-env/verify.sh
Compare to reference files ...
Check add-01 ... OK
Check addi-01 ... OK
Check and-01 ... OK
Check andi-01 ... OK
Check auipc-01 ... OK
Check beq-01 ... OK
Check bge-01 ... OK
Check bgeu-01 ... OK
Check blt-01 ... OK
Check bltu-01 ... OK
Check bne-01 ... OK
Check fence-01 ... OK
Check jal-01 ... OK
Check jalr-01 ... OK
Check lb-align-01 ... OK
Check lbu-align-01 ... OK
Check lh-align-01 ... OK
Check lhu-align-01 ... OK
Check lui-01 ... OK
Check lw-align-01 ... OK
Check or-01 ... OK
Check ori-01 ... OK
Check sb-align-01 ... OK
Check sh-align-01 ... OK
Check sll-01 ... OK
Check slli-01 ... OK
Check slt-01 ... OK
Check slti-01 ... OK
Check sltiu-01 ... OK
Check sltu-01 ... OK
Check sra-01 ... OK
Check srai-01 ... OK
Check srl-01 ... OK
Check srli-01 ... OK
Check sub-01 ... OK
Check sw-align-01 ... OK
Check xor-01 ... OK
Check xori-01 ... OK
--------------------------------
OK: 38/38 RISCV_TARGET=srv32 RISCV_DEVICE=I XLEN=32
make[3]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2'
make[3]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2'
============================ VARIABLE INFO ==================================
ROOTDIR: /home/t123/srv32/tests/riscv-arch-test.v2 [origin: file]
WORK: /home/t123/srv32/tests/riscv-arch-test.v2/work [origin: environment]
TARGETDIR: /home/t123/srv32/tests/riscv-arch-test.v2/riscv-target [origin: environment]
RISCV_TARGET: srv32 [origin: command line]
XLEN: 32 [origin: environment]
RISCV_DEVICE: M [origin: command line]
=============================================================================
make -j1 \
RISCV_TARGET=srv32 \
RISCV_DEVICE=M \
run -C /home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/M
make[4]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/M'
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/div-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/div-01.log
Excuting 3242 instructions, 3248 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.126 s
Simulation cycles: 3259
Simulation speed : 0.0258651 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/divu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/divu-01.log
Excuting 3926 instructions, 3932 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.14 s
Simulation cycles: 3943
Simulation speed : 0.0281643 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mul-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mul-01.log
Excuting 3226 instructions, 3232 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.154 s
Simulation cycles: 3243
Simulation speed : 0.0210584 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulh-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulh-01.log
Excuting 3230 instructions, 3236 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.14 s
Simulation cycles: 3247
Simulation speed : 0.0231929 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhsu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhsu-01.log
Excuting 3538 instructions, 3544 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.132 s
Simulation cycles: 3555
Simulation speed : 0.0269318 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhu-01.log
Excuting 3922 instructions, 3928 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.134 s
Simulation cycles: 3939
Simulation speed : 0.0293955 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/rem-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/rem-01.log
Excuting 3230 instructions, 3236 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.135 s
Simulation cycles: 3247
Simulation speed : 0.0240519 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/remu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/remu-01.log
Excuting 3922 instructions, 3928 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.127 s
Simulation cycles: 3939
Simulation speed : 0.0310157 MHz
make[4]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/M'
riscv-test-env/verify.sh
Compare to reference files ...
Check div-01 ... OK
Check divu-01 ... OK
Check mul-01 ... OK
Check mulh-01 ... OK
Check mulhsu-01 ... OK
Check mulhu-01 ... OK
Check rem-01 ... OK
Check remu-01 ... OK
--------------------------------
OK: 8/8 RISCV_TARGET=srv32 RISCV_DEVICE=M XLEN=32
make[3]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2'
make[2]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2'
make[1]: Leaving directory '/home/t123/srv32/tests'
make[1]: Entering directory '/home/t123/srv32/sw'
make -C common
make[2]: Entering directory '/home/t123/srv32/sw/common'
riscv-none-elf-gcc -march=rv32im_zicsr -mabi=ilp32 -misa-spec=2.2 -march=rv32im -c -o startup.o startup.S
riscv-none-elf-gcc -O3 -Wall -march=rv32im_zicsr -mabi=ilp32 -misa-spec=2.2 -march=rv32im -nostartfiles -nostdlib -c -o syscall.o syscall.c
riscv-none-elf-ar rcs libsys.a *.o
make[2]: Leaving directory '/home/t123/srv32/sw/common'
make[2]: Entering directory '/home/t123/srv32/sw/sip2'
riscv-none-elf-gcc -O3 -Wall -march=rv32im_zicsr -mabi=ilp32 -misa-spec=2.2 -march=rv32im -nostartfiles -nostdlib -L../common -o sip2.elf sip2.c -lc -lm -lgcc -lsys -T ../common/default.ld
riscv-none-elf-objcopy -j .text -O binary sip2.elf imem.bin
riscv-none-elf-objcopy -j .data -O binary sip2.elf dmem.bin
riscv-none-elf-objcopy -O binary sip2.elf memory.bin
riscv-none-elf-objdump -d sip2.elf > sip2.dis
riscv-none-elf-readelf -a sip2.elf > sip2.symbol
make[2]: Leaving directory '/home/t123/srv32/sw/sip2'
make[1]: Leaving directory '/home/t123/srv32/sw'
make[1]: Entering directory '/home/t123/srv32/sim'
Excuting 1266 instructions, 1874 cycles, 1.480 CPI
Program terminate
- ../rtl/../testbench/testbench.v:434: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.168 s
Simulation cycles: 1885
Simulation speed : 0.0112202 MHz
make[1]: Leaving directory '/home/t123/srv32/sim'
make[1]: Entering directory '/home/t123/srv32/tools'
./rvsim --memsize 128 -l trace.log ../sw/sip2/sip2.elf
The target1 insert position is 2
The target2 insert position is 1
The target3 insert position is 4
Excuting 8419 instructions, 11581 cycles, 1.376 CPI
Program terminate
Simulation statistics
=====================
Simulation time : 0.007 s
Simulation cycles: 11581
Simulation speed : 1.640 MHz
make[1]: Leaving directory '/home/t123/srv32/tools'
Compare the trace between RTL and ISS simulator
Files sim/trace.log and tools/trace.log differ
make: *** [Makefile:121: sip2] Error 1
```
:::
### Q2: Leetcode [122. Best Time to Buy and Sell Stock II](https://leetcode.com/problems/best-time-to-buy-and-sell-stock-ii/)
```
$ make test_v=2 tests 122
```
:::spoiler result
```
make coverage=0 clean && make rv32c=0 memsize=1716 -C sim; make rv32c=0 -C tools
make[1]: Entering directory '/home/t123/srv32'
for i in sw sim tools tests coverage; do \
make test_v=2 -C $i clean; \
done
make[2]: Entering directory '/home/t123/srv32/sw'
for i in pi_pthread perf irq hello pi sip2 sip qsort sem coremark 122 dhrystone common; do \
if [ -f $i/Makefile ]; then \
make -C $i clean; \
fi; \
done
make[3]: Entering directory '/home/t123/srv32/sw/pi_pthread'
rm -f *.o pi_pthread.dis pi_pthread.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/pi_pthread'
make[3]: Entering directory '/home/t123/srv32/sw/perf'
rm -f *.o perf.dis perf.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/perf'
make[3]: Entering directory '/home/t123/srv32/sw/irq'
rm -f *.o irq.elf irq.dis irq.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/irq'
make[3]: Entering directory '/home/t123/srv32/sw/hello'
rm -f *.o hello.elf hello.dis hello.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/hello'
make[3]: Entering directory '/home/t123/srv32/sw/pi'
rm -f *.o pi.elf pi.dis pi.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/pi'
make[3]: Entering directory '/home/t123/srv32/sw/sip2'
rm -f *.o sip2.elf sip2.dis sip2.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/sip2'
make[3]: Entering directory '/home/t123/srv32/sw/sip'
rm -f *.o sip.elf sip.dis sip.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/sip'
make[3]: Entering directory '/home/t123/srv32/sw/qsort'
rm -f *.o qsort.elf qsort.dis qsort.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/qsort'
make[3]: Entering directory '/home/t123/srv32/sw/sem'
rm -f *.o sem.dis sem.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/sem'
make[3]: Entering directory '/home/t123/srv32/sw/coremark'
rm -f ./coremark.elf ./*.log *.info ./index.html
rm -f coremark.dis coremark.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/coremark'
make[3]: Entering directory '/home/t123/srv32/sw/122'
rm -f *.o 122.elf 122.dis 122.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/122'
make[3]: Entering directory '/home/t123/srv32/sw/dhrystone'
rm -f *.o dhrystone.elf dhrystone.dis dhrystone.symbol [id]mem.bin memory.bin
make[3]: Leaving directory '/home/t123/srv32/sw/dhrystone'
make[3]: Entering directory '/home/t123/srv32/sw/common'
rm -f startup.o syscall.o libsys.a
make[3]: Leaving directory '/home/t123/srv32/sw/common'
make[2]: Leaving directory '/home/t123/srv32/sw'
make[2]: Entering directory '/home/t123/srv32/sim'
make[2]: Leaving directory '/home/t123/srv32/sim'
make[2]: Entering directory '/home/t123/srv32/tools'
rm -f rvsim.o decompress.o syscall.o elfread.o getch.o dump.txt trace.log trace.log.dis rvsim out.bin
if [ 0 = 0 ]; then \
rm -f -rf html coverage.info *.gcda *.gcno *.gcov; \
fi
make[2]: Leaving directory '/home/t123/srv32/tools'
make[2]: Entering directory '/home/t123/srv32/tests'
rm -rf riscv-arch-test.v2/work
make[2]: Leaving directory 'Still working on it/home/t123/srv32/tests'
make[2]: Entering directory '/home/t123/srv32/coverage'
make[2]: Leaving directory '/home/t123/srv32/coverage'
make[1]: Leaving directory '/home/t123/srv32'
make[1]: Entering directory '/home/t123/srv32/sim'
verilator -O3 -cc -Wall -Wno-STMTDLY -Wno-UNUSED +define+MEMSIZE=1716 --trace-fst --Mdir sim_cc --build --exe sim_main.cpp getch.cpp -o sim -f filelist.txt ../rtl/top.v
make[2]: Entering directory '/home/t123/srv32/sim/sim_cc'
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o getch.o ../getch.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o sim_main.o ../sim_main.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o verilated.o /home/t123/verilator/include/verilated.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o verilated_dpi.o /home/t123/verilator/include/verilated_dpi.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o verilated_fst_c.o /home/t123/verilator/include/verilated_fst_c.cpp
/usr/bin/perl /home/t123/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vriscv.cpp Vriscv___024root__DepSet_ha08c5775__0.cpp Vriscv___024root__DepSet_h309ef4e5__0.cpp Vriscv___024unit__DepSet_h6996a1c2__0.cpp Vriscv__Dpi.cpp Vriscv__Trace__0.cpp Vriscv__ConstPool_0.cpp Vriscv___024root__Slow.cpp Vriscv___024root__DepSet_ha08c5775__0__Slow.cpp Vriscv___024root__DepSet_h309ef4e5__0__Slow.cpp Vriscv___024unit__Slow.cpp Vriscv___024unit__DepSet_h69b9c73c__0__Slow.cpp Vriscv__Syms.cpp Vriscv__Trace__0__Slow.cpp > Vriscv__ALL.cpp
g++ -I. -MMD -I/home/t123/verilator/include -I/home/t123/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=1 -DVM_TRACE_VCD=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable -Wno-shadow -std=gnu++14 -Os -c -o Vriscv__ALL.o Vriscv__ALL.cpp
echo "" > Vriscv__ALL.verilator_deplist.tmp
Archive ar -rcs Vriscv__ALL.a Vriscv__ALL.o
g++ getch.o sim_main.o verilated.o verilated_dpi.o verilated_fst_c.o Vriscv__ALL.a -lz -o sim
rm Vriscv__ALL.verilator_deplist.tmp
make[2]: Leaving directory '/home/t123/srv32/sim/sim_cc'
mv sim_cc/sim .
make[1]: Leaving directory '/home/t123/srv32/sim'
make[1]: Entering directory '/home/t123/srv32/tools'
gcc -c -o rvsim.o rvsim.c -O3 -g -Wall
gcc -c -o decompress.o decompress.c -O3 -g -Wall
gcc -c -o syscall.o syscall.c -O3 -g -Wall
gcc -c -o elfread.o elfread.c -O3 -g -Wall
gcc -c -o getch.o getch.c -O3 -g -Wall
gcc -O3 -g -Wall -o rvsim rvsim.o decompress.o syscall.o elfread.o getch.o
make[1]: Leaving directory '/home/t123/srv32/tools'
make memsize=1716 test_v=2 rv32c=0 -C tests tests
make[1]: Entering directory '/home/t123/srv32/tests'
if [ "2" = "1" ]; then \
if [ ! -d riscv-arch-test.v1 ]; then \
git clone -b 1.0 https://github.com/riscv/riscv-arch-test.git riscv-arch-test.v1; \
fi; \
rm -rf riscv-arch-test.v1/riscv-target/srv32; \
cp -r srv32.v1 riscv-arch-test.v1/riscv-target/srv32; \
else \
if [ ! -d riscv-arch-test.v2 ]; then \
git clone -b 2.7.4 https://github.com/riscv/riscv-arch-test.git riscv-arch-test.v2; \
fi; \
echo; \
rm -rf riscv-arch-test.v2/riscv-target/srv32; \
cp -r srv32.v2 riscv-arch-test.v2/riscv-target/srv32; \
fiStill working on it
export ROOT_SRV32=/home/t123/srv32; \
export TARGET_SIM="/home/t123/srv32/sim/sim +trace"; \
export TARGET_SWSIM="/home/t123/srv32/tools/rvsim --memsize 1716"; \
export RISCV_PREFIX=riscv-none-elf-; \
export RISCV_TARGET=srv32; \
make rv32c=0 -C riscv-arch-test.v2
make[2]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2'
============================ VARIABLE INFO ==================================
ROOTDIR: /home/t123/srv32/tests/riscv-arch-test.v2 [origin: file]
WORK: /home/t123/srv32/tests/riscv-arch-test.v2/work [origin: file]
TARGETDIR: /home/t123/srv32/tests/riscv-arch-test.v2/riscv-target [origin: file]
RISCV_TARGET: srv32 [origin: environment]
XLEN: 32 [origin: file]
RISCV_DEVICE: I [origin: file]
=============================================================================
make[3]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2'
============================ VARIABLE INFO ==================================
ROOTDIR: /home/t123/srv32/tests/riscv-arch-test.v2 [origin: file]
WORK: /home/t123/srv32/tests/riscv-arch-test.v2/work [origin: environment]
TARGETDIR: /home/t123/srv32/tests/riscv-arch-test.v2/riscv-target [origin: environment]
RISCV_TARGET: srv32 [origin: command line]
XLEN: 32 [origin: environment]
RISCV_DEVICE: I [origin: command line]
=============================================================================
make -j1 \
RISCV_TARGET=srv32 \
RISCV_DEVICE=I \
run -C /home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/I
make[4]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/I'
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/add-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/add-01.log
Excuting 3242 instructions, 3248 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.142 s
Simulation cycles: 3259
Simulation speed : 0.0229507 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/addi-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/addi-01.log
Excuting 2170 instructions, 2176 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 2187
Simulation speed : 0.0169535 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/and-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/and-01.log
Excuting 3218 instructions, 3224 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.136 s
Simulation cycles: 3235
Simulation speed : 0.0237868 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/andi-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/andi-01.log
Excuting 2170 instructions, 2176 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 2187
Simulation speed : 0.0169535 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/auipc-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/auipc-01.log
Excuting 422 instructions, 428 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.127 s
Simulation cycles: 439
Simulation speed : 0.00345669 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/beq-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/beq-01.log
Excuting 5546 instructions, 7934 cycles, 1.430 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 7945
Simulation speed : 0.0615892 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bge-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bge-01.log
Excuting 5596 instructions, 8576 cycles, 1.532 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.148 s
Simulation cycles: 8587
Simulation speed : 0.0580203 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bgeu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bgeu-01.log
Excuting 6838 instructions, 10500 cycles, 1.535 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.132 s
Simulation cycles: 10511
Simulation speed : 0.0796288 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/blt-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/blt-01.log
Excuting 5511 instructions, 8385 cycles, 1.521 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.138 s
Simulation cycles: 8396
Simulation speed : 0.0608406 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bltu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bltu-01.log
Excuting 6830 instructions, 10444 cycles, 1.529 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.134 s
Simulation cycles: 10455
Simulation speed : 0.0780224 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bne-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/bne-01.log
Excuting 5549 instructions, 9011 cycles, 1.623 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.131 s
Simulation cycles: 9022
Simulation speed : 0.0688702 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jal-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jal-01.log
Excuting 520 instructions, 722 cycles, 1.388 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.124 s
Simulation cycles: 733
Simulation speed : 0.00591129 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jalr-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/jalr-01.log
Excuting 498 instructions, 636 cycles, 1.277 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.136 s
Simulation cycles: 647
Simulation speed : 0.00475735 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lb-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lb-align-01.log
Excuting 298 instructions, 304 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.13 s
Simulation cycles: 315
Simulation speed : 0.00242308 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lbu-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lbu-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.125 s
Simulation cycles: 311
Simulation speed : 0.002488 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lh-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lh-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 311
Simulation speed : 0.00241085 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lhu-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lhu-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.135 s
Simulation cycles: 311
Simulation speed : 0.0023037 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lui-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lui-01.log
Excuting 226 instructions, 232 cycles, 1.026 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.125 s
Simulation cycles: 243
Simulation speed : 0.001944 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lw-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/lw-align-01.log
Excuting 294 instructions, 300 cycles, 1.020 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.126 s
Simulation cycles: 311
Simulation speed : 0.00246825 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/or-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/or-01.log
Excuting 3242 instructions, 3248 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.136 s
Simulation cycles: 3259
Simulation speed : 0.0239632 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/ori-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/ori-01.log
Excuting 2166 instructions, 2172 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.137 s
Simulation cycles: 2183
Simulation speed : 0.0159343 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sb-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sb-align-01.log
Excuting 618 instructions, 624 cycles, 1.009 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.127 s
Simulation cycles: 635
Simulation speed : 0.005 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sh-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sh-align-01.log
Excuting 622 instructions, 628 cycles, 1.009 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.133 s
Simulation cycles: 639
Simulation speed : 0.00480451 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sll-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sll-01.log
Excuting 498 instructions, 504 cycles, 1.012 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.13 s
Simulation cycles: 515
Simulation speed : 0.00396154 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slli-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slli-01.log
Excuting 402 instructions, 408 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.125 s
Simulation cycles: 419
Simulation speed : 0.003352 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slt-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slt-01.log
Excuting 3222 instructions, 3228 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.131 s
Simulation cycles: 3239
Simulation speed : 0.0247252 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slti-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/slti-01.log
Excuting 2166 instructions, 2172 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.134 s
Simulation cycles: 2183
Simulation speed : 0.016291 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltiu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltiu-01.log
Excuting 2650 instructions, 2656 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.135 s
Simulation cycles: 2667
Simulation speed : 0.0197556 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sltu-01.log
Excuting 3910 instructions, 3916 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.131 s
Simulation cycles: 3927
Simulation speed : 0.0299771 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sra-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sra-01.log
Excuting 502 instructions, 508 cycles, 1.011 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.135 s
Simulation cycles: 519
Simulation speed : 0.00384444 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srai-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srai-01.log
Excuting 402 instructions, 408 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.133 s
Simulation cycles: 419
Simulation speed : 0.00315038 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srl-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srl-01.log
Excuting 514 instructions, 520 cycles, 1.011 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.141 s
Simulation cycles: 531
Simulation speed : 0.00376596 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srli-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/srli-01.log
Excuting 410 instructions, 416 cycles, 1.014 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 427
Simulation speed : 0.00331008 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sub-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sub-01.log
Excuting 3262 instructions, 3268 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.133 s
Simulation cycles: 3279
Simulation speed : 0.0246541 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sw-align-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/sw-align-01.log
Excuting 602 instructions, 608 cycles, 1.009 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.133 s
Simulation cycles: 619
Simulation speed : 0.00465414 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xor-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xor-01.log
Excuting 3238 instructions, 3244 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.136 s
Simulation cycles: 3255
Simulation speed : 0.0239338 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xori-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/xori-01.log
Excuting 2186 instructions, 2192 cycles, 1.002 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.131 s
Simulation cycles: 2203
Simulation speed : 0.0168168 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/fence-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/I/fence-01.log
Excuting 106 instructions, 112 cycles, 1.056 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.136 s
Simulation cycles: 123
Simulation speed : 0.000904412 MHz
make[4]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/I'
riscv-test-env/verify.sh
Compare to reference files ...
Check add-01 ... OK
Check addi-01 ... OK
Check and-01 ... OK
Check andi-01 ... OK
Check auipc-01 ... OK
Check beq-01 ... OK
Check bge-01 ... OK
Check bgeu-01 ... OK
Check blt-01 ... OK
Check bltu-01 ... OK
Check bne-01 ... OK
Check fence-01 ... OK
Check jal-01 ... OK
Check jalr-01 ... OK
Check lb-align-01 ... OK
Check lbu-align-01 ... OK
Check lh-align-01 ... OK
Check lhu-align-01 ... OK
Check lui-01 ... OK
Check lw-align-01 ... OK
Check or-01 ... OK
Check ori-01 ... OK
Check sb-align-01 ... OK
Check sh-align-01 ... OK
Check sll-01 ... OK
Check slli-01 ... OK
Check slt-01 ... OK
Check slti-01 ... OK
Check sltiu-01 ... OK
Check sltu-01 ... OK
Check sra-01 ... OK
Check srai-01 ... OK
Check srl-01 ... OK
Check srli-01 ... OK
Check sub-01 ... OK
Check sw-align-01 ... OK
Check xor-01 ... OK
Check xori-01 ... OK
--------------------------------
OK: 38/38 RISCV_TARGET=srv32 RISCV_DEVICE=I XLEN=32
make[3]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2'
make[3]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2'
============================ VARIABLE INFO ==================================
ROOTDIR: /home/t123/srv32/tests/riscv-arch-test.v2 [origin: file]
WORK: /home/t123/srv32/tests/riscv-arch-test.v2/work [origin: environment]
TARGETDIR: /home/t123/srv32/tests/riscv-arch-test.v2/riscv-target [origin: environment]
RISCV_TARGET: srv32 [origin: command line]
XLEN: 32 [origin: environment]
RISCV_DEVICE: M [origin: command line]
=============================================================================
make -j1 \
RISCV_TARGET=srv32 \
RISCV_DEVICE=M \
run -C /home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/M
make[4]: Entering directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/M'
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/div-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/div-01.log
Excuting 3242 instructions, 3248 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.138 s
Simulation cycles: 3259
Simulation speed : 0.0236159 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/divu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/divu-01.log
Excuting 3926 instructions, 3932 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.134 s
Simulation cycles: 3943
Simulation speed : 0.0294254 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mul-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mul-01.log
Excuting 3226 instructions, 3232 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.14 s
Simulation cycles: 3243
Simulation speed : 0.0231643 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulh-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulh-01.log
Excuting 3230 instructions, 3236 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.137 s
Simulation cycles: 3247
Simulation speed : 0.0237007 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhsu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhsu-01.log
Excuting 3538 instructions, 3544 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.131 s
Simulation cycles: 3555
Simulation speed : 0.0271374 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/mulhu-01.log
Excuting 3922 instructions, 3928 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.138 s
Simulation cycles: 3939
Simulation speed : 0.0285435 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/rem-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/rem-01.log
Excuting 3230 instructions, 3236 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.139 s
Simulation cycles: 3247
Simulation speed : 0.0233597 MHz
Compile /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/remu-01.elf
Execute /home/t123/srv32/tests/riscv-arch-test.v2/work/rv32i_m/M/remu-01.log
Excuting 3922 instructions, 3928 cycles, 1.001 CPI
Program terminate
- ../rtl/../testbench/testbench.v:448: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.129 s
Simulation cycles: 3939
Simulation speed : 0.0305349 MHz
make[4]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2/riscv-test-suite/rv32i_m/M'
riscv-test-env/verify.sh
Compare to reference files ...
Check div-01 ... OK
Check divu-01 ... OK
Check mul-01 ... OK
Check mulh-01 ... OK
Check mulhsu-01 ... OK
Check mulhu-01 ... OK
Check rem-01 ... OK
Check remu-01 ... OK
--------------------------------
OK: 8/8 RISCV_TARGET=srv32 RISCV_DEVICE=M XLEN=32
make[3]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2'
make[2]: Leaving directory '/home/t123/srv32/tests/riscv-arch-test.v2'
make[1]: Leaving directory '/home/t123/srv32/tests'
make[1]: Entering directory '/home/t123/srv32/sw'
make -C common
make[2]: Entering directory '/home/t123/srv32/sw/common'
riscv-none-elf-gcc -march=rv32im_zicsr -mabi=ilp32 -misa-spec=2.2 -march=rv32im -c -o startup.o startup.S
riscv-none-elf-gcc -O3 -Wall -march=rv32im_zicsr -mabi=ilp32 -misa-spec=2.2 -march=rv32im -nostartfiles -nostdlib -c -o syscall.o syscall.c
riscv-none-elf-ar rcs libsys.a *.o
make[2]: Leaving directory '/home/t123/srv32/sw/common'
make[2]: Entering directory '/home/t123/srv32/sw/122'
riscv-none-elf-gcc -O3 -Wall -march=rv32im_zicsr -mabi=ilp32 -misa-spec=2.2 -march=rv32im -nostartfiles -nostdlib -L../common -o 122.elf 122.c -lc -lm -lgcc -lsys -T ../common/default.ld
riscv-none-elf-objcopy -j .text -O binary 122.elf imem.bin
riscv-none-elf-objcopy -j .data -O binary 122.elf dmem.bin
riscv-none-elf-objcopy -O binary 122.elf memory.bin
riscv-none-elf-objdump -d 122.elf > 122.dis
riscv-none-elf-readelf -a 122.elf > 122.symbol
make[2]: Leaving directory '/home/t123/srv32/sw/122'
make[1]: Leaving directory '/home/t123/srv32/sw'
make[1]: Entering directory '/home/t123/srv32/sim'
Excuting 797 instructions, 1253 cycles, 1.572 CPI
Program terminate
- ../rtl/../testbench/testbench.v:434: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.136 s
Simulation cycles: 1264
Simulation speed : 0.00929412 MHz
make[1]: Leaving directory '/home/t123/srv32/sim'
make[1]: Entering directory '/home/t123/srv32/tools'
./rvsim --memsize 128 -l trace.log ../sw/122/122.elf
152
Excuting 2110 instructions, 2946 cycles, 1.396 CPI
Program terminate
Simulation statistics
=====================
Simulation time : 0.001 s
Simulation cycles: 2946
Simulation speed : 3.095 MHz
make[1]: Leaving directory '/home/t123/srv32/tools'
Compare the trace between RTL and ISS simulator
Files sim/trace.log and tools/trace.log differ
make: *** [Makefile:121: 122] Error 1
```
:::
## Requirement 2
**Explore srv32’s static branch predictor and branch penalty**
I refer the following Lab3 documents.
* [Analyze srv32 RV32 core](https://hackmd.io/@sysprog/S1Udn1Xtt#Analyze-srv32-RV32-core) - [Branch penalty](https://hackmd.io/@sysprog/S1Udn1Xtt#Branch-penalty)
* [Analyze the waveform](https://hackmd.io/@sysprog/S1Udn1Xtt#Analyze-the-waveform) - [Control Hazard](https://hackmd.io/@sysprog/S1Udn1Xtt#Control-hazards)
[`srv32` is a 3-stage pipeline architecture with IF/ID, EX, WB stages. The follwing diagram marks some important signals for later discussion.](https://hackmd.io/@sysprog/S1Udn1Xtt#Pipeline-architecture)
In this section, I choose 9 signals to analysis the branch. Signals are `next_pc`, `fetch_pc`, `if_pc`, `ex_pc`, `wb_pc`, `branch_taken`, `ex_flush` and `wb_flush`.
### Q1: Leetcode [35. Search Insert Position](https://leetcode.com/problems/search-insert-position/)
I choose Q1 in my hw3 for analysis.
In this section of the `main`, we can see the branch instruction `bge`.
```
00000090 <main>:
...
120: fce6dee3 bge a3,a4,fc <main+0x6c>
124: 00070613 mv a2,a4
128: 00040593 mv a1,s0
12c: 09098513 addi a0,s3,144 # 20090 <environ+0x4>
130: 078000ef jal ra,1a8 <printf>
134: 00448493 addi s1,s1,4
138: fb241ae3 bne s0,s2,ec <main+0x5c>
13c: 03c12083 lw ra,60(sp)
140: 03812403 lw s0,56(sp)
144: 03412483 lw s1,52(sp)
148: 03012903 lw s2,48(sp)
14c: 02c12983 lw s3,44(sp)
150: 00000513 li a0,0
154: 04010113 addi sp,sp,64
158: 00008067 ret
15c: 00160713 addi a4,a2,1
160: f8e6dee3 bge a3,a4,fc <main+0x6c>
164: fc1ff06f j 124 <main+0x94>
...
```
`srv32` static branch predictor guess it will TAKEN, but it NOT TAKEN, so the instructions will been flush.
| | | IF/ID | EX | WB |
| ------- | ---------------------- | ------- | ----- | ----- |
| next_pc | fetch_pc (immem_addr) | if_pc | ex_pc | wb_pc |
| xxx | bge a3,a4,fc | addi a4,a2,1 | bge a3,a4,fc | |
In terms of cycles, as shown below.
| PC | Instruction | cycle 1 | c2 | c3 | c4 | c5 | c6 |
| -- | --------------- | ------- | ----- | ----- | --- | --- | -- |
| 120 | bge a3,a4,fc | IF/ID | EX | WB | | | |
| 15c | addi a4,a2,1 | | NOP | NOP | NOP | | |
| 160 | bge a3,a4,fc | | | NOP | NOP | NOP | |
| xxx | exec if branch taken | | | |IF/ID| EX | WB |
### Q2: Leetcode [122. Best Time to Buy and Sell Stock II](https://leetcode.com/problems/best-time-to-buy-and-sell-stock-ii/)
I choose Q2 in my hw3 for analysis.
In this section of the `maxProfit`, we can see the branch instruction `bge`.
```
0000003c <maxProfit>:
3c: 00100793 li a5,1
40: 0cb7d263 bge a5,a1,104 <maxProfit+0xc8>
44: 00300793 li a5,3
48: 0cb7d263 bge a5,a1,10c <maxProfit+0xd0>
4c: ffc58713 addi a4,a1,-4
...
```
```
0001039c <exit>:
1039c: 0ff57793 zext.b a5,a0
103a0: 90000737 lui a4,0x90000
103a4: 02f70623 sb a5,44(a4) # 9000002c <_stack+0x8ffc002c>
103a8: 0000006f j 103a8 <exit+0xc>
```
`srv32` static branch predictor guess it will TAKEN, but it NOT TAKEN, so the instructions will been flush.
| | | IF/ID | EX | WB |
| ------- | ---------------------- | ------- | ----- | ----- |
| next_pc | fetch_pc (imem_addr) | if_pc | ex_pc | wb_pc |
| sb a5,44(a4) | lui a4,0x90000 | zext.b a5,a0 | bge a5,a1,104 | li a5,1 |
In terms of cycles, as shown below.
| PC | Instruction | cycle 1 | c2 | c3 | c4 | c5 | c6 |
| ----- | --------------- | ------- | ----- | ----- | --- | --- | -- |
| 040 | bge a5,a1,104 | IF/ID | EX | WB | | | |
| 1039c | addi a4,a2,1 | | NOP | NOP | NOP | | |
| 103a0 | bge a3,a4,fc | | | NOP | NOP | NOP | |
| xxx | exec if branch taken | | | |IF/ID| EX | WB |
### Q3: Leetcode [1290. Convert Binary Number in a Linked List to Integer](https://leetcode.com/problems/convert-binary-number-in-a-linked-list-to-integer/)
I picked [鄭至崴's assignment 3](https://hackmd.io/@Fo7UsdePRsKPVV4CPYGbpA/rydAP0OSo#Assignment3-SoftCPU) [requirement 1 C code program](https://hackmd.io/@Fo7UsdePRsKPVV4CPYGbpA/rydAP0OSo#C-code).
:::spoiler C code
```clike=
#include <stdlib.h>
#include <stdio.h>
const int array[3] = {1, 0, 1};
struct ListNode
{
int val;
struct ListNode *next;
};
void create_list(struct ListNode **cur){
for(int i = 0 ; i < 3 ; i++){
struct ListNode *new_node = (struct ListNode *)malloc(sizeof(struct ListNode));
new_node->val = array[i];
new_node->next = NULL;
*cur = new_node;
cur = &((*cur)->next);
}
}
int getDecimalValue(struct ListNode* head){
int ans = 0;
while(head){
ans <<= 1;
ans |= head->val;
head = head->next;
}
return ans;
}
int main(){
struct ListNode *head = NULL;
int ans;
create_list(&head);
ans = getDecimalValue(head);
if(ans == 5){
printf("correct!\n");
}else{
printf("wrong\n");
}
return 0;
}
```
:::
:::spoiler Makefile
```
include ../common/Makefile.common
EXE = .elf
SRC = 1290.c
CFLAGS += -L../common
LDFLAGS += -T ../common/default.ld
TARGET = 1290
OUTPUT = $(TARGET)$(EXE)
.PHONY: all clean
all: $(TARGET)
$(TARGET): $(SRC)
$(CC) $(CFLAGS) -o $(OUTPUT) $(SRC) $(LDFLAGS)
$(OBJCOPY) -j .text -O binary $(OUTPUT) imem.bin
$(OBJCOPY) -j .data -O binary $(OUTPUT) dmem.bin
$(OBJCOPY) -O binary $(OUTPUT) memory.bin
$(OBJDUMP) -d $(OUTPUT) > $(TARGET).dis
$(READELF) -a $(OUTPUT) > $(TARGET).symbol
clean:.
```
:::
:::spoiler Assembly
```
0000003c <create_list>:
3c: ff010113 addi sp,sp,-16
40: 00812423 sw s0,8(sp)
44: 00050413 mv s0,a0
48: 00800513 li a0,8
4c: 00112623 sw ra,12(sp)
50: 00912223 sw s1,4(sp)
54: 01212023 sw s2,0(sp)
58: 0e8000ef jal ra,140 <malloc>
5c: 00050493 mv s1,a0
60: 00100913 li s2,1
64: 00a42023 sw a0,0(s0)
68: 0124a023 sw s2,0(s1)
6c: 0004a223 sw zero,4(s1)
70: 00800513 li a0,8
74: 0cc000ef jal ra,140 <malloc>
78: 00050413 mv s0,a0
7c: 00042023 sw zero,0(s0)
80: 00042223 sw zero,4(s0)
84: 0084a223 sw s0,4(s1)
88: 00800513 li a0,8
8c: 0b4000ef jal ra,140 <malloc>
90: 01252023 sw s2,0(a0)
94: 00052223 sw zero,4(a0)
98: 00c12083 lw ra,12(sp)
9c: 00a42223 sw a0,4(s0)
a0: 00812403 lw s0,8(sp)
a4: 00412483 lw s1,4(sp)
a8: 00012903 lw s2,0(sp)
ac: 01010113 addi sp,sp,16
b0: 00008067 ret
000000b4 <getDecimalValue>:
b4: 00050793 mv a5,a0
b8: 00000513 li a0,0
bc: 00078e63 beqz a5,d8 <getDecimalValue+0x24>
c0: 0007a703 lw a4,0(a5)
c4: 0047a783 lw a5,4(a5)
c8: 00151513 slli a0,a0,0x1
cc: 00e56533 or a0,a0,a4
d0: fe0798e3 bnez a5,c0 <getDecimalValue+0xc>
d4: 00008067 ret
d8: 00008067 ret
000000dc <main>:
dc: fe010113 addi sp,sp,-32
e0: 00c10513 addi a0,sp,12
e4: 00112e23 sw ra,28(sp)
e8: f55ff0ef jal ra,3c <create_list>
ec: 00c12783 lw a5,12(sp)
f0: 02078263 beqz a5,114 <main+0x38>
f4: 00000713 li a4,0
f8: 0007a683 lw a3,0(a5)
fc: 0047a783 lw a5,4(a5)
100: 00171713 slli a4,a4,0x1
104: 00d76733 or a4,a4,a3
108: fe0798e3 bnez a5,f8 <main+0x1c>
10c: 00500793 li a5,5
110: 02f70063 beq a4,a5,130 <main+0x54>
114: 00020537 lui a0,0x20
118: 02c50513 addi a0,a0,44 # 2002c <_impure_ptr+0x10>
11c: 12d000ef jal ra,a48 <puts>
120: 01c12083 lw ra,28(sp)
124: 00000513 li a0,0
128: 02010113 addi sp,sp,32
12c: 00008067 ret
130: 00020537 lui a0,0x20
134: 02050513 addi a0,a0,32 # 20020 <_impure_ptr+0x4>
138: 111000ef jal ra,a48 <puts>
13c: fe5ff06f j 120 <main+0x44>
```
:::
:::spoiler Terminal infomation
```
make[1]: Entering directory '/home/t123/srv32/sw'
make -C common
make[2]: Entering directory '/home/t123/srv32/sw/common'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/t123/srv32/sw/common'
make[2]: Entering directory '/home/t123/srv32/sw/1290'
riscv-none-elf-gcc -O3 -Wall -march=rv32im_zicsr -mabi=ilp32 -misa-spec=2.2 -march=rv32im -nostartfiles -nostdlib -L../common -o 1290.elf 1290.c -lc -lm -lgcc -lsys -T ../common/default.ld
riscv-none-elf-objcopy -j .text -O binary 1290.elf imem.bin
riscv-none-elf-objcopy -j .data -O binary 1290.elf dmem.bin
riscv-none-elf-objcopy -O binary 1290.elf memory.bin
riscv-none-elf-objdump -d 1290.elf > 1290.dis
riscv-none-elf-readelf -a 1290.elf > 1290.symbol
make[2]: Leaving directory '/home/t123/srv32/sw/1290'
make[1]: Leaving directory '/home/t123/srv32/sw'
make[1]: Entering directory '/home/t123/srv32/sim'
correct!
Excuting 1404 instructions, 1894 cycles, 1.349 CPI
Program terminate
- ../rtl/../testbench/testbench.v:434: Verilog $finish
Simulation statistics
=====================
Simulation time : 0.034 s
Simulation cycles: 1905
Simulation speed : 0.0560294 MHz
make[1]: Leaving directory '/home/t123/srv32/sim'
make[1]: Entering directory '/home/t123/srv32/tools'
./rvsim --memsize 128 -l trace.log ../sw/1290/1290.elf
correct!
Excuting 1404 instructions, 1894 cycles, 1.349 CPI
Program terminate
Simulation statistics
=====================
Simulation time : 0.002 s
Simulation cycles: 1894
Simulation speed : 1.239 MHz
make[1]: Leaving directory '/home/t123/srv32/tools'
Compare the trace between RTL and ISS simulator
=== Simulation passed ===
```
:::
```
000000dc <main>:
...
fc: 0047a783 lw a5,4(a5)
100: 00171713 slli a4,a4,0x1
104: 00d76733 or a4,a4,a3
108: fe0798e3 bnez a5,f8 <main+0x1c>
10c: 00500793 li a5,5
110: 02f70063 beq a4,a5,130 <main+0x54>
...
```
| | | IF/ID | EX | WB |
| ------- | ---------------------- | ------- | ----- | ----- |
| next_pc | fetch_pc (imem_addr) | if_pc | ex_pc | wb_pc |
| xxx | beq a4,a5,130| li a5,5 | bnez a5,f8 <main+0x1c> | or a4,a4,a3 |
In terms of cycles, as shown below.
| PC | Instruction | cycle 1 | c2 | c3 | c4 | c5 | c6 |
| --- | -------------- | ------- | ----- | ----- | --- | --- | -- |
| 104 | or a4,a4,a3 | IF/ID | EX | WB | | | |
| 108 | bnez a5,f8 | | NOP | NOP | NOP | | |
| 10c | li a5,5 | | | NOP | NOP | NOP | |
| 110 | bge a3,a4,fc | | | NOP | NOP | NOP | |
| xxx | exec if branch taken | | | |IF/ID| EX | WB |
### Discussion
**How to implement more efficient code, minimizing the occurrence of stalls in the process.**
I think `load` and `store` instructions should not do near the `branch` instruction, because when `load` and `store` near the `branch`.
Maybe write `load` and `store` together and reduce the use of unnecessary variables, then put some adjustable instructions before and after `branch`, such as R-type instructions, or non-`lw`, `sw` I-type instructions, so as to reduce the occurrence of stall by adjusting the position.
When writing C programs, reduce the number of judgments as much as possible without breaking the logic, so that `branch` can be reduced directly and `stall` can be reduced.
For example, when making the same size comparison, use `a<b` instead of sometimes `a<b` and sometimes `b>=a`, and vice versa. Also, if it is possible to know which condition on the left or right side of the logic is easier to reach when writing the program, one should try to put the conditions that are easier to reach on the same side. I think it is easier for Branch predictor to predict correctly through a consistent concept of logic.
## Requirement 3
**Use RISC-V assembly language to write a Leetcode problem**
### Leetcode xxx
:::info
Still working on it.
:::
#### Problem discription
#### Code
:::spoiler Assembly
:::
#### Analysis
## Reference
* [Term Project 2021: Rework Assignment 3 : SoftCPU](https://hackmd.io/vbPzHp5CSGepqmhwvY0byA?view)
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