# Evaluate KianV
> 李建佑

## Goals
- Analyze the instruction set coverage of [KianV](https://github.com/splinedrive/kianRiscV)’s RV32IM and ensure it passes the tests provided in the [RISC-V Architecture Test Suite](https://github.com/riscv-non-isa/riscv-arch-test).
- Run xv6 on KianV and explore its handling mechanisms for CLINT, timer, and exceptions.

## Development Environment

$ verilator --version
Verilator 5.030 2024-10-27 rev UNKNOWN.REV

$ riscv64-unknown-elf-gcc --version
riscv64-unknown-elf-gcc (gc891d8dc2) 13.2.0

$ riscof --version
RISC-V Architectural Test Framework., version 1.25.3

$ system_profiler SPHardwareDataType
Hardware:

    Hardware Overview:

      Model Name: MacBook Pro
      Model Identifier: Mac15,10
      Model Number: FRX53TA/A
      Chip: Apple M3 Max
      Total Number of Cores: 14 (10 performance and 4 efficiency)
      Memory: 36 GB
      System Firmware Version: 11881.1.1
      OS Loader Version: 11881.1.1
      Activation Lock Status: Enabled

## Prerequisite Work
### Verilator
“Install Verilator using the Homebrew package management system.”

$ brew install verilator

Verilator is a simulator that compiles Verilog/SystemVerilog code into C++/SystemC. In this project, we need to compile KianV into a C++ model and then build an executable, allowing us to run RISC-V test instructions within the RISCV-arch-test framework.

### Riscv64-unknown-elf-gcc
Install riscv64-unknown-elf-gcc using the Homebrew package management system.

$ brew install riscv-tools

Riscv64-unknown-elf-gcc is a compiler that translates RISC-V instructions into ELF files. In this project, we need to use it to compile the RISC-V test instructions provided by Riscv-arch-test into executables, enabling both the KianV executable and the reference model to execute the RISC-V test instructions.

### RiscV-arch-test
First, you need to install the RISCOF testing framework.

$ pip3 install git+https://github.com/riscv/riscof.git

Next, clone the riscv-arch-test repository.

$ git clone https://github.com/riscv-non-isa/riscv-arch-test.git

After cloning, the top-level directory structure is as follows:

.
└── riscv-arch-test
         ├── CHANGELOG.md
         ├── CONTRIBUTION.md
         ├── COPYING.APACHE
         ├── COPYING.BSD
         ├── COPYING.CC
         ├── coverage
         ├── doc
         ├── README.md
         ├── requirements.txt
         ├── riscof-plugins
         ├── riscv-ctg
         ├── riscv-isac
         ├── riscv-test-suite
         └── spec

After cloning, we need to install riscv-ctg in the subdirectory riscv-ctg.

$ pwd
/riscv-arch-test
$ cd riscv-ctg
$ pip3 install --editable .

We need to install riscv-isac in the subdirectory riscv-isac.

$ pwd
/riscv-arch-test
$ cd riscv-isac
$ pip3 install --editable .

Next, we need to install the RISC-V reference models: Spike and SAIL.
To install Spike:

$ brew install dtc
$ git clone https://github.com/riscv-software-src/riscv-isa-sim.git
$ cd riscv-isa-sim
$ mkdir build
$ cd build
$ ../configure --prefix=/path/to/install #請更改到合適的位址
$ make
$ [sudo] make install

To install SAIL:

$ brew install gmp pkg-config zlib curl
$ curl --location https://github.com/rems-project/sail/releases/download/0.18-linux-binary/sail.tar.gz | tar xvz --directory=/path/to/install --strip-components=1
$ git clone https://github.com/riscv/sail-riscv.git
$ cd sail-riscv
$ ARCH=RV32 make
$ ARCH=RV64 make

The following is the architectural diagram of the entire Riscv-arch-test framework.

:::danger
Fix the permissions of the uploaded pictures.
:::

Let’s start with a simple example to help understand the testing framework. Suppose we are conducting a test for students. We need questions, answers, and the students’ submitted answers. These correspond to the riscv-test-suite, the reference model (such as Spike or SAIL), and the DUT model (KianV), respectively.

## KianV
The KianV open-source project provides multiple versions of the RISC-V 32IM processor architecture. In this project, we adopt the kianv_harris_pipelined_edition design, which implements a 5-stage pipelined RISC-V 32IMA processor architecture using modularized SystemVerilog.

### Archtecture

:::danger
Fix the permissions of the uploaded pictures.
:::

### Directory

.
├── config.ini
├── kianv
├── riscof_work
├── riscv-arch-test
└── sail_cSim

### riscv-arch-test
First, set up the name for the DUT (Device Under Test).

$ riscof setup --dutname=kianv
    INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
    INFO | using riscv_isac version : 0.18.0
    INFO | using riscv_config version : 3.18.3
    INFO | Setting up sample plugin requirements [Old files will be overwritten]
    INFO | Creating sample Plugin directory for [DUT]: kianv
    INFO | creating /Users/user/2024ca/kianv_riscof_test/kianv
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/model/model_platform.yaml -> /Users/user/2024ca/kianv_riscof_test/kianv
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/model/riscof_model.py -> /Users/user/2024ca/kianv_riscof_test/kianv
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/model/model_isa.yaml -> /Users/user/2024ca/kianv_riscof_test/kianv
    INFO | creating /Users/user/2024ca/kianv_riscof_test/kianv/__pycache__
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/model/__pycache__/riscof_model.cpython-38.pyc -> /Users/user/2024ca/kianv_riscof_test/kianv/__pycache__
    INFO | creating /Users/user/2024ca/kianv_riscof_test/kianv/env
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/model/env/model_test.h -> /Users/user/2024ca/kianv_riscof_test/kianv/env
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/model/env/link.ld -> /Users/user/2024ca/kianv_riscof_test/kianv/env
    INFO | Creating sample Plugin directory for [REF]: sail_cSim
    INFO | creating /Users/user/2024ca/kianv_riscof_test/sail_cSim
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/sail_cSim/__init__.py -> /Users/user/2024ca/kianv_riscof_test/sail_cSim
    INFO | creating /Users/user/2024ca/kianv_riscof_test/sail_cSim/__pycache__
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/sail_cSim/__pycache__/__init__.cpython-38.pyc -> /Users/user/2024ca/kianv_riscof_test/sail_cSim/__pycache__
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/sail_cSim/__pycache__/riscof_sail_cSim.cpython-38.pyc -> /Users/user/2024ca/kianv_riscof_test/sail_cSim/__pycache__
    INFO | creating /Users/user/2024ca/kianv_riscof_test/sail_cSim/env
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/sail_cSim/env/model_test.h -> /Users/user/2024ca/kianv_riscof_test/sail_cSim/env
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/sail_cSim/env/link.ld -> /Users/user/2024ca/kianv_riscof_test/sail_cSim/env
    INFO | copying /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscof/Templates/setup/sail_cSim/riscof_sail_cSim.py -> /Users/user/2024ca/kianv_riscof_test/sail_cSim
    INFO | Creating Sample Config File
    INFO | **NOTE**: Please update the paths of the reference and plugins in the config.ini file

Next, copy the test data.

$ riscof --verbose info arch-test --clone
    INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
    INFO | using riscv_isac version : 0.18.0
    INFO | using riscv_config version : 3.18.3
    INFO | Cloning repository at /Users/user/2024ca/kianv_riscof_test/riscv-arch-test
    INFO | Cloned version 3.9.1 of the repository with commit hash eb66181dd27ff7847e2c3a010705b13490b0bf75 

After configuring the necessary files for RISCOF, use the appropriate command to validate whether the files comply with the required specifications.

$ riscof validateyaml --config=config.ini
    INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
    INFO | using riscv_isac version : 0.18.0
    INFO | using riscv_config version : 3.18.3
    INFO | Reading configuration from: /Users/user/2024ca/kianv_riscof_test/config.ini
    INFO | Preparing Models
    INFO | Input-ISA file
    INFO | ISACheck: Loading input file: /Users/user/2024ca/kianv_riscof_test/kianv/kianv_isa.yaml
    INFO | ISACheck: Load Schema /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscv_config/schemas/schema_isa.yaml
    INFO | ISACheck: Processing Hart:0
    INFO | ISACheck: Initiating Validation for Hart:0
    INFO | ISACheck: No errors for Hart:0
    INFO | ISACheck:  Updating fields node for each CSR in Hart:0
    INFO | ISACheck: Dumping out Normalized Checked YAML: /Users/user/2024ca/kianv_riscof_test/riscof_work/kianv_isa_checked.yaml
    INFO | Input-Platform file
    INFO | Loading input file: /Users/user/2024ca/kianv_riscof_test/kianv/kianv_platform.yaml
    INFO | Load Schema /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscv_config/schemas/schema_platform.yaml
    INFO | Initiating Validation
    INFO | No Syntax errors in Input Platform Yaml. :)
    INFO | Dumping out Normalized Checked YAML: /Users/user/2024ca/kianv_riscof_test/riscof_work/kianv_platform_checked.yaml

After ensuring the configuration files are correct, proceed to generate the test cases.

$ riscof testlist --config=config.ini \
                --suite=riscv-arch-test/riscv-test-suite/ \
                --env=riscv-arch-test/riscv-test-suite/env
    INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
    INFO | using riscv_isac version : 0.18.0
    INFO | using riscv_config version : 3.18.3
    INFO | Generating database for suite: /Users/user/2024ca/kianv_riscof_test/riscv-arch-test/riscv-test-suite
    INFO | Database File Generated: /Users/user/2024ca/kianv_riscof_test/riscof_work/database.yaml
    INFO | Env path set to/Users/user/2024ca/kianv_riscof_test/riscv-arch-test/riscv-test-suite/env
    INFO | Reading configuration from: /Users/user/2024ca/kianv_riscof_test/config.ini
    INFO | Preparing Models
    INFO | Input-ISA file
    INFO | ISACheck: Loading input file: /Users/user/2024ca/kianv_riscof_test/kianv/kianv_isa.yaml
    INFO | ISACheck: Load Schema /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscv_config/schemas/schema_isa.yaml
    INFO | ISACheck: Processing Hart:0
    INFO | ISACheck: Initiating Validation for Hart:0
    INFO | ISACheck: No errors for Hart:0
    INFO | ISACheck:  Updating fields node for each CSR in Hart:0
    INFO | ISACheck: Dumping out Normalized Checked YAML: /Users/user/2024ca/kianv_riscof_test/riscof_work/kianv_isa_checked.yaml
    INFO | Input-Platform file
    INFO | Loading input file: /Users/user/2024ca/kianv_riscof_test/kianv/kianv_platform.yaml
    INFO | Load Schema /opt/homebrew/anaconda3/envs/risc-v/lib/python3.8/site-packages/riscv_config/schemas/schema_platform.yaml
    INFO | Initiating Validation
    INFO | No Syntax errors in Input Platform Yaml. :)
    INFO | Dumping out Normalized Checked YAML: /Users/user/2024ca/kianv_riscof_test/riscof_work/kianv_platform_checked.yaml
    INFO | Selecting Tests.

Finally, execute the tests.
The results indicate that riscv32-unknown-elf-objdump is missing, which means the riscv32-unknown-elf toolchain is not installed. I attempted to install the riscv32-unknown-elf toolchain.
The results show that riscv32-unknown-elf could not be found. I have also tried various methods found online but still couldn’t install it correctly.

Additionally, I tried using riscv64-unknown-elf with parameters to configure the 32-bit version but was unsuccessful. I also attempted using riscv-none-elf, but it did not work either.
## xv6

## Reference
[make instruction introduce](https://hackmd.io/@sysprog/SySTMXPvl)
[Verilator Manual](https://verilator.org/guide/latest/index.html)
[explain FemtoRV32 RISC-V verilog code](https://www.youtube.com/watch?v=VEQL5bJeWB0&list=PLbtzT1TYeoMiKup6aoQc3V_d7OvOKc3P5)
[explain xv6 kernel](https://www.youtube.com/watch?v=fWUJKH0RNFE&list=PLbtzT1TYeoMhTPzyTZboW_j7TPAnjv9XB)