# 5-stage pipeline RISC-V core
> 盧尚毅
## Description
Rewrite [ca2023-lab3](https://github.com/sysprog21/ca2023-lab3) to implement the complete RV32I instruction set using Chisel. The processor must pass the tests from [RISC-V Architecture Test](https://github.com/riscv-non-isa/riscv-arch-test). Subsequently, refactor the design into a 5-stage pipeline with support for bypassing. Additionally, select at least 3 RISC-V programs from the course assignments, modify them as needed, and ensure they run correctly on your improved processor.
[RV32I, RV64I Instructions](https://msyksphinz-self.github.io/riscv-isadoc/html/rvi.html)
## Finishing Lab3
[description](https://hackmd.io/@sysprog/r1mlr3I7p#Lab3-Construct-a-single-cycle-RISC-V-CPU-with-Chisel)
[GitHub](https://github.com/sysprog21/ca2023-lab3)
### Setting up the environment required for the program
adding scala to environment variables
```
vim ~/.bashrc
export PATH="~/.cache/scalacli/local-repo/bin/scala-cli/scala-cli:$PATH"
```
test `sbt run`
=>error occurs, download SDK and JDK
:::danger
Fix the permissions of uploaded pictures!
:::
downloading SDK
`curl -s "https://get.sdkman.io" | bash`
open new terminal and executing
`source "/home/cosbi/.sdkman/bin/sdkman-init.sh"`
`sdk install java $(sdk list java | grep -o "\b8\.[0-9]*\.[0-9]*\-tem" | head -1)`
If there are many Java versions, you can modify the default version using these commands.
```
// checking default java version now //
java -version
// output:
// openjdk version "11.0.21" 2023-10-17
// OpenJDK Runtime Environment Temurin-11.0.21+9 (build 11.0.21+9)
// OpenJDK 64-Bit Server VM Temurin-11.0.21+9 (build 11.0.21+9, mixed mode)
// changing default java version //
sdk default java 8.0.432-tem
// output:
// setting java 8.0.432-tem as the default version for all shells.
// checking java version again //
java -version
// output
// openjdk version "1.8.0_432"
// OpenJDK Runtime Environment (Temurin)(build 1.8.0_432-b06)
// OpenJDK 64-Bit Server VM (Temurin)(build 25.432-b06, mixed mode)
```
changing java version to 11
`sdk install java 11.0.21-tem`
time will cost a little long
`sdk install sbt`
`sbt run`
`sbt`
ref: https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master
### Initinal step
get repo
`git clone https://github.com/sysprog21/ca2023-lab3`
`cd ca2023-lab3`
run command below to check environment
`sbt test`
run test without changing code in folder
### Debug
Run the `sbt test` command to run every test case.
identifying the code that needs to be modified using error messages
ex:
```
should recursively calculate Fibonacci(10) *** FAILED ***
[info] firrtl.passes.PassExceptions: firrtl.passes.CheckInitialization$RefNotInitializedException: @[src/main/scala/riscv/core/InstructionDecode.scala 127:14] : [module InstructionDecode] Reference io is not fully initialized.
[info] : io.memory_write_enable <= VOID
```
According to error message above, we can modified `io.memory_write_enable <= VOID` in file `InstructionDecode.scala`
### Adding and modifying the program to ensure it runs smoothly
`InstructionFetch.scala`
checking program counter can move to correct location
```scala
// lab3(InstructionFetch) begin
when(io.jump_flag_id) {
pc := io.jump_address_id
}.otherwise {
pc := pc + 4.U
}
// lab3(InstructionFetch) end
```
`InstructionDecode.scala`
controlling read and write signals by comparing opcode values
```scala
// lab3(InstructionDecode) begin
io.memory_read_enable := opcode === InstructionTypes.L
io.memory_write_enable := opcode === InstructionTypes.S
// lab3(InstructionDecode) end
```
`Execute.scala`
utilizing the opcode value to connect the input source
```scala
// lab3(Execute) begin
// Connect alu_control and alu to carry out an alu operation.
alu.io.func := alu_ctrl.io.alu_funct
// Attach the Execute output to the alu input.(*Note that the ALU operation signals cause different input connections.*)
alu.io.op1 := Mux( io.aluop1_source === 0.U, io.reg1_data, io.instruction_address)
alu.io.op2 := Mux( io.aluop2_source === 0.U, io.reg2_data, io.immediate)
// lab3(Execute) end
```
`CPU.scala`
connecting input and output of execute stage
```scala
// lab3(cpu) begin
ex.io.instruction := inst_fetch.io.instruction
ex.io.instruction_address := inst_fetch.io.instruction_address
ex.io.reg1_data := regs.io.read_data1
ex.io.reg2_data := regs.io.read_data2
ex.io.immediate := id.io.ex_immediate
ex.io.aluop1_source := id.io.ex_aluop1_source
ex.io.aluop2_source := id.io.ex_aluop2_source
// lab3(cpu) end
```
### Pass messages
#### InstructionFetchTest
#### InstructionDecoderTest
#### ExecuteTest
#### All Test
## riscv-arch-test
[riscv-arch-test](https://github.com/riscv-non-isa/riscv-arch-test)
[docs](https://riscof.readthedocs.io/en/stable/installation.html)
[ELF file](https://security-onigiri.github.io/2018/03/08/the-101-of-elf-binaries-on-linux-understanding-and-analysis.html)
### Constructing environment
**Install Python**
```
sudo apt-get install python3.6
pip3 install --upgrade pip
```
To avoid encountering an unknown issue while working on this project.
I decided to download Miniconda in order to obtain the Python 3.6 environment.
provided by ChatGPT
```
// install conda
wget https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh
bash Miniconda3-latest-Linux-x86_64.sh
// initinalize or activate conda
source ~/miniconda3/bin/activate
// check python version
conda search python
// create new environment
conda create -n RISCOF python=3.6
// get into new environment
conda activate RISCOF
// exit environment
conda deactivate
// remove env
conda remove --name RISCOF --all
```
#### Install RISCOF
ubuntu22.04 and python3.6
* easy way
`pip3 install riscof`
* unknown error
```
pip3 install git+https://github.com/riscv/riscof.git
```
Installing the aforementioned instructions will place the riscof folder path at the address shown below.
`~/miniconda3/envs/RISCOF/lib/python3.6/site-packages/`
`cd ~/miniconda3/envs/RISCOF/lib/python3.6/site-packages/`
**Install riscv-ctg**
But I can't find riscv-ctg folder, I skip this step first.
```
cd riscv-ctg
pip3 install --editable .
```
**Install riscv-isac**
```
cd riscv-isac
pip3 install --editable .
```
```
cd ~/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_isac
pip3 install --editable .
// Obtaining file:///home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_isac
// ERROR: file:///home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_isac does not appear to be a Python project: neither 'setup.py' nor 'pyproject.toml' found.
```
**Because the project of `github.com/riscv/riscof.git` lacks of riscv-ctg and `setup.py`, I try to change `github.com/riscv/riscof.git` with `https://github.com/riscv-non-isa/riscv-arch-test.git` and reset environment.**
`pip3 install git+https://github.com/riscv-non-isa/riscv-arch-test.git`
```
Collecting git+https://github.com/riscv-non-isa/riscv-arch-test.git
Cloning https://github.com/riscv-non-isa/riscv-arch-test.git to /tmp/pip-req-build-yiwjouy8
Running command git clone --filter=blob:none -q https://github.com/riscv-non-isa/riscv-arch-test.git /tmp/pip-req-build-yiwjouy8
Resolved https://github.com/riscv-non-isa/riscv-arch-test.git to commit 1b1fb26da37a2a426dd1f5260b0f08ff4e321f0e
ERROR: git+https://github.com/riscv-non-isa/riscv-arch-test.git does not appear to be a Python project: neither 'setup.py' nor 'pyproject.toml' found.
```
**git clone `https://github.com/riscv-non-isa/riscv-arch-test.git` and move specific folders(riscv-isac, riscv-ctg) into `~/miniconda3/envs/RISCOF/lib/python3.6/site-packages/`**
```
~/Documents$ git clone https://github.com/riscv-non-isa/riscv-arch-test.git
~/Documents$ cd riscv-arch-test/
~/Documents/riscv-arch-test$cp -r riscv-ctg ~/miniconda3/envs/RISCOF/lib/python3.6/site-packages/
~/Documents/riscv-arch-test$cp -r riscv-isac ~/miniconda3/envs/RISCOF/lib/python3.6/site-packages/
cd ~/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg
pip3 install --editable .
```
<details>
<summary>error message</summary>
<pre><code>
Obtaining file:///home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg
Preparing metadata (setup.py) ... error
ERROR: Command errored out with exit status 1:
command: /home/cosbi/miniconda3/envs/RISCOF/bin/python -c 'import io, os, sys, setuptools, tokenize; sys.argv[0] = '"'"'/home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg/setup.py'"'"'; __file__='"'"'/home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg/setup.py'"'"';f = getattr(tokenize, '"'"'open'"'"', open)(__file__) if os.path.exists(__file__) else io.StringIO('"'"'from setuptools import setup; setup()'"'"');code = f.read().replace('"'"'\r\n'"'"', '"'"'\n'"'"');f.close();exec(compile(code, __file__, '"'"'exec'"'"'))' egg_info --egg-base /tmp/pip-pip-egg-info-xd8qkthh
cwd: /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg/
Complete output (7 lines):
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg/setup.py", line 51, in <module>
install_requires=read_requires(),
File "/home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg/setup.py", line 17, in read_requires
with open(os.path.join(here, "riscv_ctg/requirements.txt"),"r") as reqfile:
FileNotFoundError: [Errno 2] No such file or directory: '/home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg/riscv_ctg/requirements.txt'
----------------------------------------
WARNING: Discarding file:///home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv-ctg. Command errored out with exit status 1: python setup.py egg_info Check the logs for full command output.
ERROR: Command errored out with exit status 1: python setup.py egg_info Check the logs for full command output.
</code></pre>
</details>
**try using local environment instead of miniconda**
fail!
#### Using `riscof`
if install successfully. run `riscof` can show message below.
#### Install RISCV-GNU Toolchain
```
sudo apt-get install autoconf automake autotools-dev curl python3 libmpc-dev \
libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool \
patchutils bc zlib1g-dev libexpat-dev
git clone --recursive https://github.com/riscv/riscv-gnu-toolchain
```
After a little while, cloning riscv-gnu-toolchain will appear as follows if it was successful.
```
git clone --recursive https://github.com/riscv/riscv-opcodes.git
cd riscv-gnu-toolchain
./configure --prefix=/path/to/install --with-arch=rv32gc --with-abi=ilp32d # for 32-bit toolchain ## make sure to change '/path/to/install' to path you want to install(absolute path)
make
```
adding `/path/to/install/bin` to environment variables.
Use these commands to verify the successful installation of gnu-chain.
```
riscv32-unknown-elf-addr2line riscv32-unknown-elf-elfedit
riscv32-unknown-elf-ar riscv32-unknown-elf-g++
riscv32-unknown-elf-as riscv32-unknown-elf-gcc
riscv32-unknown-elf-c++ riscv32-unknown-elf-gcc-8.3.0
riscv32-unknown-elf-c++filt riscv32-unknown-elf-gcc-ar
riscv32-unknown-elf-cpp riscv32-unknown-elf-gcc-nm
riscv32-unknown-elf-gcc-ranlib riscv32-unknown-elf-gprof
riscv32-unknown-elf-gcov riscv32-unknown-elf-ld
riscv32-unknown-elf-gcov-dump riscv32-unknown-elf-ld.bfd
riscv32-unknown-elf-gcov-tool riscv32-unknown-elf-nm
riscv32-unknown-elf-gdb riscv32-unknown-elf-objcopy
riscv32-unknown-elf-gdb-add-index riscv32-unknown-elf-objdump
riscv32-unknown-elf-ranlib riscv32-unknown-elf-readelf
riscv32-unknown-elf-run riscv32-unknown-elf-size
riscv32-unknown-elf-strings riscv32-unknown-elf-strip
```
#### Install Spike
[Spike](https://github.com/riscv-software-src/riscv-isa-sim)
```
$ sudo apt-get install device-tree-compiler
$ git clone https://github.com/riscv-software-src/riscv-isa-sim.git
$ cd riscv-isa-sim
$ mkdir build
$ cd build
$ mkdir ~/Spike
$ ../configure --prefix=/path/to/install
$ // ../configure --prefix=~/Spike
$ make
$ [sudo] make install
```
successfully
#### Install SAIL (SAIL C-emulator)
```
$ sudo apt-get install libgmp-dev pkg-config zlib1g-dev curl
$ curl --location https://github.com/rems-project/sail/releases/download/0.18-linux-binary/sail.tar.gz | [sudo] tar xvz --directory=/path/to/install --strip-components=1
```
adding `/path/to/install/bin` to environment variables.
Then build the RISC-V Sail Model:
```
$ git clone https://github.com/riscv/sail-riscv.git
$ cd sail-riscv
$ ARCH=RV32 make
$ ARCH=RV64 make
// add these paths in your $PATH or an alias to it to execute them from command line
$ ln -s sail-riscv/c_emulator/riscv_sim_RV64 /usr/bin/riscv_sim_RV64
$ ln -s sail-riscv/c_emulator/riscv_sim_RV32 /usr/bin/riscv_sim_RV32
```
### Checking riscof running status
activate environment and create a new `config.ini`.
```
$ cd ~/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof
$ conda activate RISCOF
$ riscof setup --dutname=spike
```
expected output
```
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Setting up sample plugin requirements [Old files will be overwritten]
INFO | Creating sample Plugin directory for [DUT]: spike
INFO | Creating sample Plugin directory for [REF]: sail_cSim
INFO | Creating Sample Config File
INFO | **NOTE**: Please update the paths of the reference and plugins in the config.ini file
```
rewrite `~/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/config.ini`
```diff
[RISCOF]
ReferencePlugin=sail_cSim
ReferencePluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/sail_cSim
DUTPlugin=spike
DUTPluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/spike
[spike]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/spike
ispec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/spike/spike_isa.yaml
pspec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/spike/spike_platform.yaml
target_run=1
[sail_cSim]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/sail_cSim
+ PATH=/home/cosbi/sail-riscv/c_emulator/
```
run `riscof --verbose info run --config ./config.ini --suite ~/riscv-arch-test/riscv-test-suite/rv32i_m/ --env ~/riscv-arch-test/riscv-test-suite/env` to test if riscof execute successfully.
<details>
<summary>output message</summary>
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Reading configuration from: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/config.ini
INFO | Preparing Models
INFO | Input-ISA file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/spike/spike_isa.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_isa.yaml
INFO | Processing Hart: hart0
INFO | Initiating Validation
INFO | No errors for Hart: 0 :)
INFO | Updating fields node for each CSR
INFO | Initiating WARL legality checks.
INFO | Initiating post processing and reset value checks.
INFO | Initiating validation checks for indexed csrs
INFO | Initiating validation checks for shadow fields
INFO | Performing Checks on PMP CSRs
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/riscof_work/spike_isa_checked.yaml
INFO | Input-Platform file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/spike/spike_platform.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_platform.yaml
INFO | Initiating Validation
INFO | No Syntax errors in Input Platform Yaml. :)
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/riscof_work/spike_platform_checked.yaml
INFO | Generating database for suite: /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m
INFO | Database File Generated: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/riscof_work/database.yaml
INFO | Env path set to/home/cosbi/riscv-arch-test/riscv-test-suite/env
INFO | Running Build for DUT
INFO | Running Build for Reference
INFO | Selecting Tests.
INFO | Running Tests on DUT.
INFO | Running Tests on Reference Model.
INFO | Initiating signature checking.
INFO | Following 92 tests have been run :
INFO | TEST NAME : COMMIT ID : STATUS
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cadd-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi16sp-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/caddi4spn-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cand-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/candi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbeqz-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cbnez-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cebreak-01.S : 136ab593b08af9ea3081f822767e44d4133d301d : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cj-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjal-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjalr-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cjr-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clui-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clw-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/clwsp-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cmv-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cnop-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cor-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cslli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrai-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csrli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csub-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/csw-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cswsp-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/cxor-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/misalign1-cjalr-01.S : 0bf9236d18b17643c2d367e3be92d676c0c3a36f : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/C/src/misalign1-cjr-01.S : 0bf9236d18b17643c2d367e3be92d676c0c3a36f : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S : 81c7a2b769baa2f33f40bc5455299b1362b5d125 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/misalign1-jalr-01.S : 0c4cdffe19b1a48d9fec8590c8817af2ff924a37 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/div-01.S : 9b503d7890296e53aa8a06e49ebef3c61ce5d3fd : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/divu-01.S : 3c7e9d41d4efb9dcb9c0af83e0eecbe28327bf3c : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mul-01.S : 3c7e9d41d4efb9dcb9c0af83e0eecbe28327bf3c : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulh-01.S : 3c7e9d41d4efb9dcb9c0af83e0eecbe28327bf3c : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhsu-01.S : a02feaee118fbea01fbb8fdcdf62bce6f7067478 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/mulhu-01.S : 3c7e9d41d4efb9dcb9c0af83e0eecbe28327bf3c : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/rem-01.S : 3c7e9d41d4efb9dcb9c0af83e0eecbe28327bf3c : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/M/src/remu-01.S : 3c7e9d41d4efb9dcb9c0af83e0eecbe28327bf3c : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/Zifencei/src/Fencei.S : 274b6cd787d4d5b0b6c41424b9b7dcca495a9d4b : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/ebreak.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/ecall.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-beq-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bge-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bgeu-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-blt-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bltu-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-bne-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-lh-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-lhu-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-lw-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-sh-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign-sw-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign2-jalr-01.S : bb74a4aefaa8c89fb28b876484cfdf9ca020cec1 : Passed
INFO | Test report generated at /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/riscof_work/report.html.
INFO | Opening test report in web-browser
</details>
test report
### Runing test
#### Create Neccesary Env Files
[reference](https://hackmd.io/@ivywang2015/rvvm-riscof)
[使用 RISCOF 測試 rv32emu](https://hackmd.io/@Risheng/RISCOF)
**initialize config**
```
// enter the RISCOF environment
source ~/miniconda/bin/activate
conda activate RISCOF
// since this project tests the chisel CPU using sbt
riscof setup --dutname=sbt
```
<details>
<summary>output message</summary>
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Setting up sample plugin requirements [Old files will be overwritten]
INFO | Creating sample Plugin directory for [DUT]: sbt
INFO | Creating sample Plugin directory for [REF]: sail_cSim
INFO | Creating Sample Config File
INFO | **NOTE**: Please update the paths of the reference and plugins in the config.ini file
</details>
**get `riscv-arch-test` repo**
```
cd ~
riscof --verbose info arch-test --clone
```
<details>
<summary>output message</summary>
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Clonning repository at /home/cosbi/riscv-arch-test
INFO | Clonned version 3.9.1 of the repository with commit hash eb66181dd27ff7847e2c3a010705b13490b0bf75
</details>
config.ini
```
[RISCOF]
ReferencePlugin=sail_cSim
ReferencePluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sail_cSim
DUTPlugin=sbt
// change this to path of `which sbt`
DUTPluginPath=/home/cosbi/.sdkman/candidates/sbt/current/bin/sbt
[sbt]
// change this to path of `which sbt`
pluginpath=/home/cosbi/.sdkman/candidates/sbt/current/bin/sbt
ispec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_isa.yaml
pspec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_platform.yaml
target_run=1
[sail_cSim]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sail_cSim
```
first try:
<details>
<summary>error message</summary>
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Reading configuration from: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/config.ini
INFO | Preparing Models
ERROR | Error while importing sbt.
ERROR | No module named 'riscof_sbt'eb66181dd27ff7847e2c3a010705b13490b0bf75
</details>
change `sbt/riscof_sbt.py` line 22
```
class sbt(pluginTemplate):
__model__ = "sbt"
#TODO: please update the below to indicate family, version, etc of your DUT.
__version__ = "1.10.5"
```
change `config.ini` back to original generated format
```diff
[RISCOF]
ReferencePlugin=sail_cSim
ReferencePluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sail_cSim
DUTPlugin=sbt
- DUTPluginPath=/home/cosbi/.sdkman/candidates/sbt/current/bin/sbt
+ DUTPluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt
[sbt]
- pluginpath=/home/cosbi/.sdkman/candidates/sbt/current/bin/sbt
+ pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt
ispec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_isa.yaml
pspec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_platform.yaml
target_run=1
[sail_cSim]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sail_cSim
```
<details>
<summary>output message</summary>
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Reading configuration from: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/config.ini
INFO | Preparing Models
INFO | Input-ISA file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_isa.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_isa.yaml
INFO | Processing Hart: hart0
INFO | Initiating Validation
INFO | No errors for Hart: 0 :)
INFO | Updating fields node for each CSR
INFO | Initiating WARL legality checks.
INFO | Initiating post processing and reset value checks.
INFO | Initiating validation checks for indexed csrs
INFO | Initiating validation checks for shadow fields
INFO | Performing Checks on PMP CSRs
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/riscof_work/sbt_isa_checked.yaml
INFO | Input-Platform file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_platform.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_platform.yaml
INFO | Initiating Validation
INFO | No Syntax errors in Input Platform Yaml. :)
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/riscof_work/sbt_platform_checked.yaml
INFO | Generating database for suite: /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m
INFO | Database File Generated: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/riscof_work/database.yaml
INFO | Env path set to/home/cosbi/riscv-arch-test/riscv-test-suite/env
INFO | Running Build for DUT
INFO | Running Build for Reference
ERROR | riscv_sim_RV32: executable not found. Please check environment setup.
</details>
using `find /home/cosbi -name riscv_sim_RV32` to find location of `riscv_sim_RV32`, adding this address to `config.ini` can solve error of `ERROR | riscv_sim_RV32: executable not found. Please check environment setup.`
```diff
[RISCOF]
ReferencePlugin=sail_cSim
ReferencePluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sail_cSim
DUTPlugin=sbt
DUTPluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt
[sbt]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt
ispec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_isa.yaml
pspec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sbt/sbt_platform.yaml
target_run=1
[sail_cSim]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/sail_cSim
+ PATH=/home/cosbi/sail-riscv/c_emulator/
```
<details>
<summary>error message</summary>
ERROR | [warn] No sbt.version set in project/build.properties, base directory: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/riscof_work/C/src/cadd-01.S/dut
[info] welcome to sbt 1.10.5 (Eclipse Adoptium Java 11.0.21)
[info] set current project to dut (in build file:/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_for_riscv_arch_test/riscof_work/C/src/cadd-01.S/dut/)
[error] Expected 'info'
[error] --isa=rv32imc
[error] ^
</details>
#### run
```
riscof --verbose info run --config ./config.ini --suite ~/riscv-arch-test/riscv-test-suite/rv32i_m --env ~/riscv-arch-test/riscv-test-suite/env
```
## Updating Lab3 to meet the requirements of the riscv-arch-test
[github](https://github.com/lu1215/5-stage-pipeline-RISC-V-core/tree/main)
### Setting `riscof`
```
$ mkdir riscv-arch-test
$ cd riscv-arch-test
$ riscof setup --refname=sail_cSim --dutname=chisel_CPU
$ vim config.ini
```
```diff
[RISCOF]
ReferencePlugin=sail_cSim
ReferencePluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/sail_cSim
DUTPlugin=chisel_CPU
DUTPluginPath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU
[chisel_CPU]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU
ispec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU/chisel_CPU_isa.yaml
pspec=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU/chisel_CPU_platform.yaml
target_run=1
[sail_cSim]
pluginpath=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/sail_cSim
+ PATH=/home/cosbi/sail-riscv/c_emulator/
```
### Rewrite scala test
#### adding new test file
`src/test/scala/riscv/riscv_arch_test/RiscvArchTest.scala`
#### Rewrite `riscof_chisel_CPU.py`
change cmd for test chisel CPU
```diff
- self.dut_exe = os.path.join(config['PATH'] if 'PATH' in config else "","chisel_CPU")
+ self.dut_exe = f'sbt "testOnly riscv.riscv_arch_test.RiscvArchTest -- -DelfFile={{elfFile}}"'
```
only test I instruction
```diff
self.isa = 'rv' + self.xlen
if "I" in ispec["ISA"]:
self.isa += 'i'
- if "M" in ispec["ISA"]:
- self.isa += 'm'
- if "F" in ispec["ISA"]:
- self.isa += 'f'
- if "D" in ispec["ISA"]:
- self.isa += 'd'
- if "C" in ispec["ISA"]:
- self.isa += 'c'
```
changing test instruction
```diff
- if self.target_run:
- # set up the simulation command. Template is for spike. Please change.
- simcmd = self.dut_exe + ' --isa={0} +signature={1} +signature-granularity=4 {2}'.format(self.isa, sig_file, elf)
- else:
- simcmd = 'echo "NO RUN"'
+ elf = os.path.join(test_dir, elf)
+ if self.target_run:
+ sbt_cmd = (
+ f'sbt -DelfFile={elf} -DsignatureFile={sig_file} "testOnly riscv.riscv_arch_test.RiscvArchTest"'
+ )
+ else:
+ sbt_cmd = 'echo "NO RUN"'
```
changing location of executing testing command
```diff
- execute = '@cd {0}; {1}; {2};'.format(testentry['work_dir'], cmd, simcmd)
+ execute = '@cd {0}; {1}; cd {2}; {3};'.format(testentry['work_dir'], cmd, "/home/cosbi/Documents/5-stage-pipeline-RISC-V-core", sbt_cmd)
```
run `riscof --verbose info run --config ./config.ini --suite ~/riscv-arch-test/riscv-test-suite/rv32i_m/I --env ~/riscv-arch-test/riscv-test-suite/env`
<details>
<summary>output message</summary>
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Reading configuration from: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/config.ini
INFO | Preparing Models
INFO | Input-ISA file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU/chisel_CPU_isa.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_isa.yaml
INFO | Processing Hart: hart0
INFO | Initiating Validation
INFO | No errors for Hart: 0 :)
INFO | Updating fields node for each CSR
INFO | Initiating WARL legality checks.
INFO | Initiating post processing and reset value checks.
INFO | Initiating validation checks for indexed csrs
INFO | Initiating validation checks for shadow fields
INFO | Performing Checks on PMP CSRs
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/chisel_CPU_isa_checked.yaml
INFO | Input-Platform file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU/chisel_CPU_platform.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_platform.yaml
INFO | Initiating Validation
INFO | No Syntax errors in Input Platform Yaml. :)
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/chisel_CPU_platform_checked.yaml
INFO | Generating database for suite: /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I
INFO | Database File Generated: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/database.yaml
INFO | Env path set to/home/cosbi/riscv-arch-test/riscv-test-suite/env
INFO | Running Build for DUT
INFO | Running Build for Reference
INFO | Selecting Tests.
INFO | Running Tests on DUT.
INFO | Running Tests on Reference Model.
INFO | Initiating signature checking.
INFO | Following 39 tests have been run :
INFO | TEST NAME : COMMIT ID : STATUS
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S : 81c7a2b769baa2f33f40bc5455299b1362b5d125 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/misalign1-jalr-01.S : 0c4cdffe19b1a48d9fec8590c8817af2ff924a37 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
INFO | Test report generated at /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/report.html.
INFO | Opening test report in web-browser
</details>
report:
**all output is 0**
#### test another method to run riscof test
1. change `riscof_chisel_CPU.py`
```diff
- + execute = '@cd {0}; {1}; cd {2}; {3};'.format(testentry['work_dir'], cmd, "/home/cosbi/Documents/5-stage-pipeline-RISC-V-core", sbt_cmd)
+ execute = '@cd {0}; {1}; cd {2}; riscv32-unknown-elf-objcopy -O binary {3} src/main/resources/test.asmbin ; {4};'.format(testentry['work_dir'], cmd, "/home/cosbi/Documents/5-stage-pipeline-RISC-V-core", elf, sbt_cmd)
```
this step will generate a `test.asmbin` file in `src/main/resources`
2. rewrite `src/test/scala/riscv/riscv_arch_test/RiscvArchTest.scala`.
when run `sbt_cmd` `src/test/scala/riscv/riscv_arch_test/RiscvArchTest.scala` will call `riscv32-unknown-elf-readelf -s $elfFile` to get address of `begin_signature` and `end_signature`, and then CPU will get input file(`test.asmbin`) and run, when execution of instructions is end, the program will write contents of memory between the address of `begin_signature` and `end_signature`.
finally, `riscof` compare `DUT-chisel_CPU.signature` and `Reference-sail_c_simulator.signature` to check pass or fail.
**but outputs are still `0`**
* **solution**
checking all data in memory and I found that location for storing instruction was different from location of .elf file, and then I changed the range of memory dump( relative address ), and get right output.
<details>
<summary>output message</summary>
INFO | ****** RISCOF: RISC-V Architectural Test Framework 1.25.3 *******
INFO | using riscv_isac version : 0.18.0
INFO | using riscv_config version : 3.7.2
INFO | Reading configuration from: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/config.ini
INFO | Preparing Models
INFO | Input-ISA file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU/chisel_CPU_isa.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_isa.yaml
INFO | Processing Hart: hart0
INFO | Initiating Validation
INFO | No errors for Hart: 0 :)
INFO | Updating fields node for each CSR
INFO | Initiating WARL legality checks.
INFO | Initiating post processing and reset value checks.
INFO | Initiating validation checks for indexed csrs
INFO | Initiating validation checks for shadow fields
INFO | Performing Checks on PMP CSRs
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/chisel_CPU_isa_checked.yaml
INFO | Input-Platform file
INFO | Loading input file: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscv-arch-test/chisel_CPU/chisel_CPU_platform.yaml
INFO | Load Schema /home/cosbi/miniconda3/envs/RISCOF/lib/python3.6/site-packages/riscv_config/schemas/schema_platform.yaml
INFO | Initiating Validation
INFO | No Syntax errors in Input Platform Yaml. :)
INFO | Dumping out Normalized Checked YAML: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/chisel_CPU_platform_checked.yaml
INFO | Generating database for suite: /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I
INFO | Database File Generated: /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/database.yaml
INFO | Env path set to/home/cosbi/riscv-arch-test/riscv-test-suite/env
INFO | Running Build for DUT
INFO | Running Build for Reference
INFO | Selecting Tests.
INFO | Running Tests on DUT.
INFO | Running Tests on Reference Model.
INFO | Initiating signature checking.
INFO | Following 39 tests have been run :
INFO | TEST NAME : COMMIT ID : STATUS
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S : 81c7a2b769baa2f33f40bc5455299b1362b5d125 : Passed
ERROR | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Failed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/misalign1-jalr-01.S : 0c4cdffe19b1a48d9fec8590c8817af2ff924a37 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | /home/cosbi/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S : b91f98f3a0e908bad4680c2e3901fbc24b63a563 : Passed
INFO | Test report generated at /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/report.html.
INFO | Opening test report in web-browser
</details>
### Alter the CPU so that every instruction test passes
Since B-type and `jalr` have failed conditions, it seems that the `5-stage-pipeline-RISC-V-core/src/main/scala/riscv/core/Execute.scala` file may have the bug.
```scala
io.if_jump_address := io.immediate + Mux(opcode === Instructions.jalr, io.reg1_data, io.instruction_address)
```
I am still trying to figure out why, but I have noticed that if the test assembly code includes the `jal register, 0x8xxxxxxx`, all memory dumps become "deadbeef".
#### Try to find error in waveform
using `riscv32-unknown-elf-objcopy -O binary /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/src/beq-01.S/dut/my.elf /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/src/main/resources/test.asmbin` to generate `.asmbin` of `beq`
using `WRITE_VCD=1 sbt -DelfFile=/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/src/beq-01.S/dut/my.elf -DsignatureFile=test.log "testOnly riscv.riscv_arch_test.RiscvArchTest"` to generate `.vcd` file.
using `gtkwave /home/cosbi/Documents/5-stage-pipeline-RISC-V-core/test_run_dir/Single_Cycle_CPU_RISCOF_ELF_test_should_load_ELF_homecosbiDocuments5stagepipelineRISCVcoreriscof_worksrcbeq01Sdutmyelf_extract_signature_range_and_test/TestTopModule.vcd` to open gtkwave and check waveform of `.vcd` file
double click signals to add waveform of specific signals in screen.
using `/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/doc_check_riscof/riscof_work/I/src/beq-01.S/ref/ref.disass` file which is generated by `sail`, using this file to check the value of pc is in the right address.
in `add` case, I find that waveform of instruction is as same as `/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/src/add-01.S/ref/ref.disass`
(`7D5C0837` -> `DDD80813` -> `00785893` -> `01985793`)
but in `beq` case, waveform doesn't work like `.disass` file, after execute first instruction `lui a6,0x7d5c0`, next instruction will become `nop`, and then suddenly jump to `lui a0,0x33333`.
(`7D5C0837` -> `00000013` -> `33333537` -> `00000013`)
based on observation above, I think I need to check the signal of `cpu_io_instruction`.
I check the `cpu_io_instruction_valid` signal because a lot of machine code of instruction is `0x00000013`. In the `add` case, `cpu_io_instruction_valid` becomes 1 in 13615 ps (above), and in the `beq` case, `cpu_io_instruction_valid` becomes 1 in 120103 ps (below).
there are 58329 lines in `/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/src/beq-01.S/ref/ref.disass` and 5120 lines in `/home/cosbi/Documents/5-stage-pipeline-RISC-V-core/riscof_work/src/add-01.S/ref/ref.disass`. and `cpu.io.instruction_valid := rom_loader.io.load_finished` in class `TestTopModule`,
In summary, I guess that an error of execution is caused because there are too many lines of code that must be loaded into the ROM, `rom_loader.io.load_finished` remains at 0, and `cpu.io.instruction_valid` also remains at 0.
in `beq` case (`7D5C0837` -> `00000013` -> `33333537` -> `00000013`), because class `Memory` use instruction_address as input to output instruction, and in `src/main/scala/riscv/core/InstructionFetch.scala` file, if `instruction_valid == 0`, then `pc` will remain same value, but it change its value, I think initialize `new Memory(8192)` is not enough for `beq` test, I try to change size of memory to 65536.
`output.signature` stops being entirely `deadbeef`.
try `riscof` to test `rv32i` instruction again.
Change the RAM size to 450560. since there are 439236 lines in the `jal` assembly code.
Ultimately, the chisel CPU passes every test on the rv32i.
The second command is not `00000013` or `33333537`, but the `cpu_io_instruction_valid` signal in `beq` case still becomes 1 in 120103 ps. => It has to do with memory capacity.
## Modifying Lab3 to be a 5-stage pipeline CPU
[yat CPU](https://yatcpu.sysu.tech/labs/lab3-pipelined-cpu/)
riscv-core
1. adding register to save all state variable
write a scala class named `PipelineRegister`, this register is used to save latest state control signals, and if occur stall or flush, it will change value stored in register.
Each state should have a new register to store control signals.(add IF2ID.scala, ID2EX.scala, EX2MEM.scala and MEM2WB.scala)
io in `CPU.scala`
``` diff
val regs = Module(new RegisterFile)
+ val ctrl = Module(new Control)
val inst_fetch = Module(new InstructionFetch)
+ val if2id = Module(new IF2ID)
val id = Module(new InstructionDecode)
+ val id2ex = Module(new ID2EX)
val ex = Module(new Execute)
+ val ex2mem = Module(new EX2MEM)
val mem = Module(new MemoryAccess)
+ val mem2wb = Module(new MEM2WB)
val wb = Module(new WriteBack)
+ val forwarding = Module(new Forwarding)
```
2. situation of hazard control
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