# RV32IM core running FreeRTOS
> 陳彥廷

## Building Environment
### Install verilator and gtkwave

$ sudo apt install build-essential verilator gtkwave

### Install sbt from SDKMAN

$ curl -s "https://get.sdkman.io" | bash
$ source "$HOME/.sdkman/bin/sdkman-init.sh"

### Install Eclipse Temurin JDK 11

$ sdk install java 11.0.21-tem 
$ sdk install sbt

## Test the RV32IM core

$ sbt test

The result is shown below:

[info] *** 1 TEST FAILED ***
[error] Failed tests:
[error]         riscv.singlecycle.SimpleTrapTest
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful

Try to solve the failed test case:

[info] SimpleTrapTest:
[info] Single Cycle CPU with CSR and CLINT
[info] - should jump to trap handler and then return *** FAILED ***
[info]   java.lang.NullPointerException:
[info]   at ... ()
[info]   at peripheral.InstructionROM.readAsmBinary(InstructionROM.scala:42)
[info]   at peripheral.InstructionROM.<init>(InstructionROM.scala:25)
[info]   at riscv.singlecycle.TestTopModule.$anonfun$instruction_rom$2(CPUTest.scala:30)
[info]   at chisel3.Module$.do_apply(Module.scala:53)
[info]   at riscv.singlecycle.TestTopModule.$anonfun$instruction_rom$1(CPUTest.scala:30)
[info]   at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:33)
[info]   at riscv.singlecycle.TestTopModule.<init>(CPUTest.scala:30)
[info]   at riscv.singlecycle.SimpleTrapTest.$anonfun$new$42(CPUTest.scala:125)
[info]   at ... ()
[info]   ...

> <inprogress...>

### CSR

**Introduction**

Control and Status Registers (CSRs) are essential components in computer architecture that play a crucial role in managing and monitoring the behavior of a processor or a system.

**CSR Register**

- **Machine Status (mstatus) Register**
Use to record various control and status related to “Machine state”.
It is a machine-level CSR that holds various status and control information about the machine mode.


**The Machine-mode status register (mstatus) for RV32.**

- **Machine Exception Program Counter(mepc) Register**
Use to **hold the program counter value at the time of an exception or trap in machine mode**.
- Machine Cause **(mcause) Register**
Use to hold a code or identifier that indicates the cause of an exception or interrupt.
- **“mtvec” Register**
Use to specify the base address of the trap vector table for machine-level interrupts.
- Relative **CSR Address extracted from Spec. Vol.II Page 8-10**

| Number | Privilege | Name | Description |
| --- | --- | --- | --- |
| 0x300 | MRW | mstatus | |
| 0x305 | MRW | mtvec | Machine trap-handler base address. |
| 0x341 | MRW | mepc | Machine exception program counter. |
| 0x342 | MRW | mcause | |
| 0xC00 | MRW | CycleL | |
| 0XC80 | MRW | CycleH | only in RV32 |

**CSR Operation**

- **CSRRW/CSRRWI:**

Read the value from a Control and Status Register (CSR) and write the contents of a general-purpose register into the CSR.

- **CSRRS/CSRRSI:**

Read the value from a CSR, perform a bitwise OR operation with the value in register rs1, and write the result back into the CSR.

- **CSRRC/CSRRCI:**

Read the value from a CSR, perform a bitwise AND operation with the complement (~) of the value in register rs1, and write the result back into the CSR.

- **MERT (Machine Exception Return):**

This instruction is used to return from an exception, updating the mstatus register:

- Update MIE (Machine Interrupt Enable) with the value of MPIE.
- Update the MPIE field's value to 1.

## FreeRTOs
[FreeRTOs](https://www.freertos.org/) is a market-leading embedded system RTOS supporting 40+ processor architectures with a small memory footprint, fast execution times, and cutting-edge RTOS features and libraries including Symmetric Multiprocessing (SMP), a thread-safe TCP stack with IPv6 support, and seamless integration with cloud services. It’s open-source and actively supported and maintained.
### Get FreeRTOs

git clone [e-mail]:FreeRTOS/FreeRTOS.git

## Reference
* [Single-Cycle RISC-V CPU](https://hackmd.io/zCc-wifJRyOTjTD5DHOkhQ?view#1-Environment)
* [FreeRTOs](https://www.freertos.org/)