Assignment3: SoftCPU

Due: Nov 16, 2020

Requirements

Following the instructions of Lab3: Reindeer - RISCV RV32I[M] Soft CPU, you shall modify the assembly programs used/done with Assignment1 or Assignment2 as new test case(s) for Reindeer Simulation with Verilator.
- I-ADD-01 is a good starting point for writing test cases.
- You have to ensure signature matched with the requirements described in RISC-V Compliance Tests.
Check the generated VCD file and use GTKwave to view the waveform. Then, explain how your program is executed along with Reindeer Simulation.
Write down your thoughts and progress in HackMD notes.
- Summarize how RISC-V Compliance Tests works and why the signature should be matched.
- Explain how Reindeer works with Verilator.
- What is 2 x 2 Pipeline? How can we benefit from such pipeline design?
- What is "Hold and Load"? And, how the simulation does for bootstraping?
- Can you show some signals/events inside Reindeer and describe?