RV32I[M]
Soft CPURV32I[M]
Soft CPUPulseRain Reindeer is a soft CPU of Von Neumann architecture. It supports RISC-V RV32I[M]
instruction set, and features a 2 x 2 pipeline. It strives to make a balance between speed and area, and offers a flexible choice for soft CPU across all FPGA platforms.
Reindeer's pipeline is composed of 4 stages:
However, unlike traditional pipelines, Reindeer's pipeline stages are mapped to a 2 x 2 layout, as illustrated below:
In the 2 x 2 layout, each stage is active every other clock cycle. For the even cycle, only IF and IE stages are active, while for the odd cycle, only ID and MEM stages are active. In this way, the Instruction Fetch and Memory Access always happen on different clock cycles, thus to avoid the structural hazard caused by the single port memory.
Bootstrapping a soft CPU tends to be a headache. The traditional approach is more or less like the following:
The drawbacks of the above approach are:
To break the status quo, the PulseRain Reindeer takes a different approach called "hold and load", which brings a hardware based OCD (on-chip debugger) into the fore, as illustrated below:
4.0
Expected: Verilator 4.028 2020-02-06 rev v4.026-92-g890cecc1
(or later)$PATH
Expected result: riscv-none-embed-gcc (xPack GNU RISC-V Embedded GCC x86_64) 10.2.0
Open I-ADD-01.vcd
generated by Verilator:
signal: clk
signal: clk, start, load_active, mem_access_addr
Reference: PicoSoC: How we created a RISC-V based ASIC processor using a full open-source foundry