Assignment3: single-cycle RISC-V CPU

Due: Dec 1, 2023

This assignment is quite challenging, and it is recommended that you dedicate a minimum of 3 full days to complete it. Otherwise, it may be difficult to produce a meaningful outcome.

Requirements

1. Following the instructions in Lab3: Construct a single-cycle RISC-V CPU with Chisel, engage with the Chisel Tutorial by completing the provided exercises.
   • Make sure you have already completed the exercises from Part 1 to Part 3.6 and are familiar with Chisel/Scala.
   • Avoid frequent Google searches, as the provided materials on the lab page are curated to facilitate your learning experience. Simply focus on learning by actively engaging with the prepared materials.
   • You may encounter various challenges during this process. Please review the GitHub issues and make note of your observations.
   • Describe the operation of 'Hello World in Chisel' and enhance it by incorporating logic circuit.
2. Adhering to the guidance provided in Lab3: Construct a single-cycle RISC-V CPU with Chisel, incorporate the code within the // lab3 section in src/main/scala/riscv/core/*.scala to pass the corresponding unit tests. This hands-on approach encourages you to learn by actively participating in the process, enhancing your understanding of the subject matter.
   • Refrain from copying and pasting your solution directly into the HackMD note. Instead, provide a concise summary of the various test cases, outlining the aspects of the CPU they evaluate, the techniques employed for loading test program instructions, and the outcomes of these test cases.
   • For signals involved in filling in the blanks, use the testing framework to output waveform diagrams and describe the changes in key signals of corresponding components when executing different instructions.
   • Fork the GitHub repository ca2023-lab3 and make commits that correspond to your ongoing efforts accordingly. The progress should always be publicly visible and transparent. $\to$ Read the GitHub documentation, such as Fork a repo.
3. Modify the handwritten RISC-V assembly code in Homework2 to ensure it functions correctly on the single-cycle RISC-V CPU aka "MyCPU" designed during Lab3: Construct a single-cycle RISC-V CPU with Chisel. Keep the modified code in the csrc directory.
   • Extend the Scala code in src/test/scala/riscv/singlecycle/CPUTest.scala to include additional test items related to your modified RISC-V assembly program. Ensure you compile it into an ELF file, which will later be converted into a binary file using the objcopy utility. Refer to the FibonacciTest as an example to see how to extend the ChiselScalatestTester for testing the src/main/resources/fibonacci.asmbin program.
   • Execute your program using Verilator and analyze the signals by examining the waveform diagrams. Describe the variations in key signals of the respective components when different instructions are executed.
   • To ensure compatibility between the programs used in Homework2 and MyCPU, you should remove the RDCYCLE/RDCYCLEH instructions. Alternatively, you can expand the CPU's functionality by implementing the relevant CSR instructions, which would enable the execution of RDCYCLE/RDCYCLEH instructions on MyCPU.
4. Write down your thoughts and progress in HackMD notes.
   • Of course, you MUST write in English.
   • Avoid using screenshots that solely contain plain text. Here are the reasons why:
     • Text-based content is more efficiently searchable than having to browse through images iteratively.
     • The rendering engine of HackMD can consistently generate well-structured layouts with annotated text instead of relying on arbitrary pictures.
     • It provides a more accessible and user-friendly experience for individuals with visual impairments.
5. BONUS: Enhance MyCPU to provide improved ecall/break support, enabling RISC-V programs to make system calls similar to the functionalities available in rv32emu.

Fill in the table for your homework

Pay attention to spacing: separate each item with |. This means there should be exactly two single space characters both before and after the | character.

Formal (given) name	HackMD note
廖泓博	Homework3
黃柏叡	Homework3
陳金諄	Homework3
張澤家	Homework3
洪胤勛	Homework3
洪佑杭	Homework3
侯廷翰	Homework3
盧俊銘	Homework3
李冠澄	Homework3
鍾沅熹	Homework3
洪碩星	Homework3
魏泳禎	Homework3
楊宇翔	Homework3
林柏全	Homework3
倪英智	Homework3
劉智恩	Homework3
蕭明祥	Homework3
陳彥佑	Homework3
陳燦仁	Homework3
戴鈞彥	Homework3
廖華鑫	Homework3
李承泰	Homework3
林子勝	Homework3
簡志耀	Homework3
林允顥	Homework3
蔡忠翰	Homework3 $\to$ Publish a Note with Permalink. Check the URL carefully.
施柏安	Homework3
高紹捷	Homework3
李熙堃	Homework3
鄭吉廷	Homework3
林勁羽	Homework3
陳川曜	Homework3
吳堉銨	Homework3
邱德昌	Homework3
鄭朝駿	Homework3
李晨瑞	Homework3
江冠霆	Homework3
鄭博文	Homework3
李亮穎	Homework3
陸品潔	Homework3
丁竟烽	Homework3
王豊惟	Homework3
陳浩文	Homework3
唐飴苹	Homework3
張偉治	Homework3
林昊霆	Homework3
黃于睿	Homework3
周育晨	Homework3
許唯萱	Homework3
張正德	Homework3
林晉宇	Homework3
黃定山	Homework3
范紘維	Homework3
陳冠元	Homework3
顏伯丞	Homework3
曾鼎棊	Homework3
彭煜博	Homework3
謝維倫	Homework3
魏彥庭	Homework3 $\to$ Publish a Note with Permalink. Check the URL carefully.
施宇庭	Homework3
張智惟	Homework3

Be aware of spaces. Separate each item with |