# Assignment3: single-cycle RISC-V CPU
contributed by < [hugo0406](https://github.com/hugo0406/ca2023-lab3) >

## Hello World in Chisel

 class Hello extends Module {
  val io = IO(new Bundle {
    val led = Output(UInt(1.W))
  })
  val CNT_MAX = (50000000 / 2 - 1).U;
  val cntReg  = RegInit(0.U(32.W))
  val blkReg  = RegInit(0.U(1.W))
  cntReg := cntReg + 1.U
  when(cntReg === CNT_MAX) {
    cntReg := 0.U
    blkReg := ~blkReg                                   
  }
  io.led := blkReg
}

### Explanation
Observe the module,we can find that there is only 1 output `led`. It's not difficult to discern its purpose from the output name.The counter `cntReg` will increment by one every clock cycle . When the condition `cntReg === CNT_MAX` is met, `cntReg` will reset to zero ,and `blkReg` will reverse.The module shows a blinking LED.

### Enhancement

class Hello extends Module {
  val io = IO(new Bundle {
    val led = Output(UInt(1.W))
  })
  val CNT_MAX = (50000000 / 2 - 1).U;
  val cntReg  = RegInit(0.U(32.W))
  val blkReg  = RegInit(0.U(1.W))
  cntReg := cntReg + 1.U
  cntReg := Mux(cntReg === CNT_MAX,0.U,cntReg )
  blkReg := Mux(cntReg === CNT_MAX,~blkReg,blkReg)
  io.led := blkReg

## Lab3: Construct a single-cycle CPU with Chisel
We just need to add some line of code to four Scala files to complete the implementation.After completing each module, perform a single test.
- InstructionFetch.scala
- InstructionDecode.scala
- Execute.scala
- CPU.scala

By carefully understanding the diagram below and observing the ports of each module, you can quickly complete this part and pass all tests.

**Single-cycle CPU architecture diagram**

### InstructionFetch
If a `jump_flag_id` is set, which means jump is required ,the PC is directed to the jump address; otherwise, it is incremented to PC + 4.

### InstructionDecode
- Observe all output ports of the InstructionDecode Module,can found that except `memory_read_enable` and `memory_write_enable`, have been completed.
- Only load/store instructions have a memory access stage.
- If it is an **L-type** instruction,the control signal `memory_read_enable` is set to 1
- If it is an **S-type** instruction,the control signal `memory_write_enable` is set to 1.

### Execute
- We need to assign values to the input ports of ALU. ALU inputs are depends on `ALUOp1Src` and `ALUOp2Src` this two control signal.The controls signal `ALUFunct` to control the ALU function.
- `alu.io.op1`:determined by `ALUOp1Src`, it determines whether they are register data or the instruction address
- `alu.io.op2`:determined by `ALUOp2Src` ,it determines whether they are register data or the immediate

### CPU
- Observe the input port of the Execute module.
- instruction
- instruction_address
- reg1_data
- reg2_data
- immediate
- aluop1_source
- aluop2_source
- There are a total of six input ports. All we need to do is establish connections between the inputs of the Execute module and the outputs of other modules.

### Pass all tests

$ sbt test 

Output:

[info] welcome to sbt 1.9.7 (Ubuntu Java 11.0.21)
[info] loading settings for project ca2023-lab3-build from plugins.sbt ...
[info] loading project definition from /home/cychn/Desktop/ca2023-lab3/project
[info] loading settings for project root from build.sbt ...
[info] set current project to mycpu (in build file:/home/cychn/Desktop/ca2023-lab3/)
[info] InstructionFetchTest:
[info] InstructionFetch of Single Cycle CPU
[info] - should fetch instruction
[info] ExecuteTest:
[info] Execution of Single Cycle CPU
[info] - should execute correctly
[info] RegisterFileTest:
[info] Register File of Single Cycle CPU
[info] - should read the written content
[info] - should x0 always be zero
[info] - should read the writing content
[info] ByteAccessTest:
[info] Single Cycle CPU
[info] - should store and load a single byte
[info] QuicksortTest:
[info] Single Cycle CPU
[info] - should perform a quicksort on 10 numbers
[info] FibonacciTest:
[info] Single Cycle CPU
[info] - should recursively calculate Fibonacci(10)
[info] InstructionDecoderTest:
[info] InstructionDecoder of Single Cycle CPU
[info] - should produce correct control signal
[info] Run completed in 1 minute, 25 seconds.
[info] Total number of tests run: 9
[info] Suites: completed 7, aborted 0
[info] Tests: succeeded 9, failed 0, canceled 0, ignored 0, pending 0
[info] All tests passed.
[success] Total time: 90 s (01:30), completed Nov 29, 2023, 10:45:18 PM

### Adapt Assignment2