HackMD
Assignment3: single-cycle RISC-V CPU
contributed by < scottgood333 >
Lab3: Construct a single-cycle RISC-V CPU with Chisel
Setting up environment
Before installing Scala build tool, we must first install a JDK.
JDK 11 is here installed.
$ sudo apt update
$ sudo apt -y install openjdk-11-jdk-headless
Following the instructions to install sbt after the JDK being installed.
$ sudo apt-get update
$ sudo apt-get install apt-transport-https curl gnupg -yqq
$ echo "deb https://repo.scala-sbt.org/scalasbt/debian all main" | sudo tee /etc/apt/sources.list.d/sbt.list
$ echo "deb https://repo.scala-sbt.org/scalasbt/debian /" | sudo tee /etc/apt/sources.list.d/sbt_old.list
$ curl -sL "https://keyserver.ubuntu.com/pks/lookup?op=get&search=0x2EE0EA64E40A89B84B2DF73499E82A75642AC823" | sudo -H gpg --no-default-keyring --keyring gnupg-ring:/etc/apt/trusted.gpg.d/scalasbt-release.gpg --import
$ sudo chmod 644 /etc/apt/trusted.gpg.d/scalasbt-release.gpg
$ sudo apt-get update
$ sudo apt-get install sbt
Installing GTKWave
$ sudo apt install gtkwave
Chisel Tutorial
Checking if the sbt works properly or not.
$ sbt run
The result is shown as below :
[info] Loading project definition from /home/scottgood333/chisel-tutorial/project
[info] Loading settings for project chisel-tutorial from build.sbt ...
[info] Set current project to chisel-tutorial (in build file:/home/scottgood333/chisel-tutorial/)
[info] running hello.Hello
[info] [0.001] Elaborating design...
[info] [0.038] Done elaborating.
Computed transform order in: 111.6 ms
Total FIRRTL Compile Time: 238.7 ms
End of dependency graph
Circuit state created
[info] [0.001] SEED 1704783997615
test Hello Success: 1 tests passed in 6 cycles taking 0.007022 seconds
[info] [0.002] RAN 1 CYCLES PASSED
[success] Total time: 2 s, completed Dec 27, 2023, 3:06:38 PM
Running other examples.
$ ./run-examples.sh FullAdder
[info] Loading project definition from /home/scottgood333/chisel-tutorial/project
[info] Loading settings for project chisel-tutorial from build.sbt ...
[info] Set current project to chisel-tutorial (in build file:/home/scottgood333/chisel-tutorial/)
[warn] Multiple main classes detected. Run 'show discoveredMainClasses' to see the list
[info] running examples.Launcher FullAdder
Starting tutorial FullAdder
[info] [0.002] Elaborating design...
[info] [0.557] Done elaborating.
Computed transform order in: 149.8 ms
Total FIRRTL Compile Time: 376.8 ms
file loaded in 0.034163814 seconds, 13 symbols, 8 statements
[info] [0.001] SEED 1704785701907
test FullAdder Success: 8 tests passed in 9 cycles in 0.010222 seconds 880.44 Hz
[info] [0.003] RAN 4 CYCLES PASSED
Tutorials passing: 1
[success] Total time: 2 s, completed Dec 27, 2023, 3:35:03 PM
Conpleting the code provided in Lab3
All unit tests passed, the results are shown as following:
[info] welcome to sbt 1.9.7 (Ubuntu Java 11.0.21)
[info] loading settings for project ca2023-lab3-build from plugins.sbt ...
[info] loading project definition from /home/scottgood333/ca2023-lab3/project
[info] loading settings for project root from build.sbt ...
[info] set current project to mycpu (in build file:/home/scottgood333/ca2023-lab3/)
[info] compiling 4 Scala sources to /home/scottgood333/ca2023-lab3/target/scala-2.13/classes ...
[warn] /home/scottgood333/ca2023-lab3/src/main/scala/riscv/core/Execute.scala:56:40: method apply in object MuxLookup is deprecated (since Chisel 3.6): Use MuxLookup(key, default)(mapping) instead
[warn] (opcode === InstructionTypes.B) && MuxLookup(
[warn] ^
[warn] /home/scottgood333/ca2023-lab3/src/main/scala/riscv/core/InstructionDecode.scala:150:19: method apply in object MuxLookup is deprecated (since Chisel 3.6): Use MuxLookup(key, default)(mapping) instead
[warn] val immediate = MuxLookup(
[warn] ^
[warn] two warnings found
[info] InstructionDecoderTest:
[info] InstructionDecoder of Single Cycle CPU
[info] - should produce correct control signal
[info] ExecuteTest:
[info] Execution of Single Cycle CPU
[info] - should execute correctly
[info] InstructionFetchTest:
[info] InstructionFetch of Single Cycle CPU
[info] - should fetch instruction
[info] ByteAccessTest:
[info] Single Cycle CPU
[info] - should store and load a single byte
[info] FibonacciTest:
[info] Single Cycle CPU
[info] - should recursively calculate Fibonacci(10)
[info] QuicksortTest:
[info] Single Cycle CPU
[info] - should perform a quicksort on 10 numbers
[info] RegisterFileTest:
[info] Register File of Single Cycle CPU
[info] - should read the written content
[info] - should x0 always be zero
[info] - should read the writing content
[info] Run completed in 17 seconds, 687 milliseconds.
[info] Total number of tests run: 9
[info] Suites: completed 7, aborted 0
[info] Tests: succeeded 9, failed 0, canceled 0, ignored 0, pending 0
[info] All tests passed.
[success] Total time: 28 s, completed Dec 29, 2023, 5:30:47 PM
Single-cycle RISC-V CPU
InstructionFetchTest
In InstructionFetch stage, using a MUX and jump_flag_id to determine whether the PC should jump to the address or increment by 4.
At this cycle, a jump occurs and the PC jump to the specific address.
At the next cycle, the PC increments by 4 while the jump_flag is 0.
InstructionDecodeTest
In InstructionDecode stage, using two MUXs and opcode to determine whether the memory_read/memory_write should be enabled or not.
At this cycle, the io_memory_write_enable is set while the io_memory_read_enable is 0.
InstructionExecuteTest
In InstructionExecute stage, two signals as the input of the ALU determines the values of alu.io.op1 and alu.io.op2.
At this cycle, io_aluop1_source and io_aluop2_source are set.
Assignment 2 Adaption(Working On)
Still working on improving the code of assignment 1,the related tasks will be completed in the near future.
