# Assignment3: SoftCPU

###### tags: `Computer Architecture`

### outline
[TOC]

### Requirement
check [here](https://hackmd.io/@sysprog/2020-arch-homework3)

### RISC-V Compliance Tests
reference to this [RISC-V Compliance Tests](https://github.com/riscv/riscv-compliance/blob/master/doc/README.adoc)
#### Purpose of compliance tests
> The goal of compliance tests is to check whether the processor under development meets the open RISC-V standards or not.

#### Running the compliance tests
at [README.md](https://github.com/riscv/riscv-compliance/blob/master/README.md) mentioned that
> The only setup required is to define where the toolchain is found, and where the target / device is found.
For the toolchain, the binaries must be in the search path and the compiler prefix is defined on the make line. The default value for this is `RISCV_PREFIX ?= riscv64-unknown-elf-`

in this homework, we use the file `imperas-riscv-tests` to test instead of `riscv-compliance`, because the behind one is lack of execute file `riscvOVPsim.exe*`, the file is located at `/home/_path/imperas-riscv-tests/riscvOVPsim.exe*`

### Create test case
Before started, we have to modified the `Makefile` to match our requirement, add the following to Makefile

RISCV_PREFIX := riscv-none-embed-
RISCV_TARGET := riscvOVPsim
RISCV_DEVICE := rv32i

and remember to modified

# export RISCV_PREFIX ?= riscv64-unknown-elf-
export RISCV_PREFIX ?= riscv-none-embed-  

that's the GNU toolchain for riscv we use in [Lab2](https://hackmd.io/@sysprog/rJAufgHYS), and we have to source it because I don't add it to `.bashrc`

$ cd $HOME
$ source riscv-none-embed-gcc/setenv

#### Modified `Makefile.include`
`Makefile.include` is at `/home/_path/imperas-riscv-tests/riscv-target/riscvOVPsim/device/rv32i`

ROOTDIR ?= /home/_path/imperas-riscv-tests
TARGET_SIM ?= /home/_path/imperas-riscv-tests/riscv-ovpsim/bin/Linux64/riscvOVPsim.exe
...
RISCV_PREFIX ?= riscv-none-embed-

* In this assignment, I'm trying to simulate the hw2 [Counting Leading Zero](https://hackmd.io/JpArAuMySz2uze4QL4CPSQ#clzc), we have to compliance the test case `.S` file into `.elf` file, first we place the `.S` file under `/home/_path/imperas-riscv-tests/riscv-test-suite/rv32i/src`, and the generated `.elf` and `.signature.output` file will be placed under `/home/_path/imperas-riscv-tests/work/rv32i`

* as we run `make`, there will generate 4 files `CLZ.elf`, `CLZ.elf.objdump`, `CLZ.signature.output`, `CLZ.log` under the path `/home/_path/imperas-riscv-tests/work/rv32i`, then we can copy them to `/home/_path/Reindeer/sim/compliance`, and run `make` at `/home/_path/Reindeer/sim/verilator`


Finally we get `CLZ.vcd`, we can trace it using the tool `gtkwave`

### Waveform of VCD file

TODO : analyze

### How [RISC-V Compliance ](https://github.com/riscv/riscv-compliance/blob/master/doc/README.adoc) Tests work

TBD

### How [Reindeer](https://github.com/PulseRain/Reindeer) works with [Verilator](https://www.veripool.org/wiki/verilator)

Verilator is a software which can convert HDL(Verilog) code to C++, at the second point in [Verilator introduction](https://www.veripool.org/wiki/verilator)
> Verilator is invoked with parameters similar to GCC or Synopsys’s VCS. It "Verilates" the specified Verilog or SystemVerilog code by reading it, performing lint checks, and optionally inserting assertion checks and coverage-analysis points. It outputs single- or multi-threaded .cpp and .h files, the "Verilated" code.

### 2 x 2 Pipeline

[introduction](https://hackmd.io/@sysprog/rJw2A5DqS)


### Hold and Load

overview