2020 Logice Design Final Exam - Verilog
===
###### tags: `verilog` `邏輯設計` `邏設` `digital design`

8(a). Suppose `Y` is a 32-bit singned binary number. Please assign `1'b1` to `Neg` if `Y` is negatvie, otherwise assign `1'b0` to it. Write down the code frament.(You are not allow to use any operator, including `&`,`|`, `+`, `if else`, `(condition)? :` ...)

input [31:0] Y;
...
assign Neg = ...;

:::info
ANS

assign Neg = Y[31];

reference: [AS4 Part 2 Review](https://hackmd.io/BL8JeVjkS4GIDIcYz5pP1w#Sample-code)
:::

---
8(b) According to the waveform, is it a mealy machine or a moore machine. Please expain the reason.


:::info
ANS
Mealy.
By definition, the output signal, `Out`, is based on the input signal, `In` and the current state.


reference: [Lab 3 Review](https://hackmd.io/bpvTZCfYSbGmjo4Nfq0t0Q#Q5-Sequence-Detector)
:::

---

8( c). Describe the following circuit using gate level description.


:::info
ANS

module Latch (clk, d, q);
  input clk;
  input d;
  output q;
  wire not_d, not_q, a1, a2;

  not  not_0 (not_d, d);
  nand nand_0(a1, d, clk);
  nand nand_1(a2, not_d, clk);
  
  nand nand_2(q, a1, not_q);
  nand nand_3(not_q, a2, q);
endmodule

reference: [as4 part 2 review q3 - code](https://hackmd.io/BL8JeVjkS4GIDIcYz5pP1w?view#Q3)

reference: [hello world in Verilog](https://hackmd.io/@dppa1008/BJWS5_B_G?type=view)

Note

- gate level description:
- `gate gate_name(output, input1, input2....)`

- re-assignment is not allowed:

not(not_q, q);
nand nand_3(not_q, a2, q);

//-> error

:::

---
9. Given a state transition diagram,
(a) What is the function of this circuit?
(b) Describe the following circuit in Verilog.


:::info
(a) detect 1101

reference [Lab3 review](https://hackmd.io/bpvTZCfYSbGmjo4Nfq0t0Q#Q5-Sequence-Detector)

(b)

`define S0 2'd0
`define S1 2'd1
`define S2 2'd2
`define S3 2'd3

module q5(clk, rst, in, out);
    input clk, rst, in;
    output out;
    reg [1:0] state, next_state;
    reg out;
    
    always@(posedge clk) begin
        if (!rst) begin
            state <= `S0;
        end else begin
            state <= next_state;
        end
    end

    always@(*)begin
        case(state)
        `S0: next_state = (in == 1'b1) ? `S1 : `S0; 
        `S1: next_state = (in == 1'b1) ? `S2 : `S0; 
        `S2: next_state = (in == 1'b1) ? `S2 : `S3; 
        `S3: next_state = (in == 1'b1) ? `S1 : `S0; 
        endcase
    end

    assign out = (state == `S3 && in == 1'b1) ? 1'b1 : 1'b0;

endmodule

reference [Lab3 review](https://hackmd.io/bpvTZCfYSbGmjo4Nfq0t0Q#Q5-Sequence-Detector)

:::