AS4 Part 2 Review
===

[TOC]

---

## Q2
- Testcase Info

- Q2-0: unsigned_test w/o +/-, flags
- Q2-1: unsinged_test w/o flags
- Q2-2: unsigned_test
- Q2-3: sample_test w/o +/-, flags
- Q2-4:  sample_test w/o flags
- Q2-5: sample_test

`w/o` : without, `w/`: with

- score
- Q2-0 : 40%
- Q2-1 : 60%
- Q2-2 : 70%
- Q2-3 : 80%
- Q2-4 : 90%
- Q2-5 : 100%

### Sample code
- [Code Link](https://www.codepile.net/pile/bODkymaE)
- Hightlights

    input signed [32 - 1:0] A, B;
    output reg signed[32 - 1:0] Y;

- We introduce a new type `signed`. Signals with `signed` will be considered as a signed number during operations (`+`, `-` ...).
- However, we suggest to use a 2's complement adder in this lab instead of `sigend` configuration. It may be helpful for you to learn Logic Design.

---

    assign Negative = Y[31];

- In 2's complement representation, the first bit denotes as signed bit. We can easily check whether `Y` is a negative number by `Y[31] == 1'b1`, or simply `Negative = Y[31]`.

### **Testbench**
<font color=#bf2222>We highly recommend to read our testbench. It will help you to learn Verilog.</font>

- [Code Link](https://www.codepile.net/pile/XRJOXavE)
- Hightlights

    module tb();
    ... 
    ALU t(.A(A), .B(B), .Y(Y), .sel(sel), .Negative(Negative), .Zero(Zero));

    always #(`CYC / 2) clk = ~clk;

    initial begin
        sel = 3'b0;
        repeat(2 ** 3) begin // 8 sel
            #0.2; unsigned_test;
            #0.2; change_sel;
        end
 
        if (`PASS == `HIGH)
            $display("[INFO] q2 PASS");
        $finish; // stop the testbench
    end

- The main part of testbench.
- `unsigned_test` is a [task](https://hackmd.io/@dppa1008/testbench#step-6) which generates 2**5 testcases and check the answers.
-

    task unsigned_test; begin
        {A, B} = {32'b0, 32'b0};
        repeat(2**5) begin
            @(posedge clk) #0.1;
                check_zero;
                check_negative;
                check_ans;
            @(negedge clk);
                {A, B} = {$urandom_range(0,500),$urandom_range(0,500)};
        end
    end
    endtask

- `change_sel` increases the `sel` signal. (`sel = sel + 1`).

---

## Q3
According to the description:
> Please design a latch module (fig. 1) and implement a clk positive edge trigger flip-flop (fig. 2).
>

You have to design a <font color=#bf2222>latch</font> and a <font color=#bf2222>D-flip-flop</font>.

Most of students did not design a "correct" latch and did not follow the circuits we gave. That's why they failed.

We will use our testbench(not released one) to verify your design. That means, passing the released testbench does not represent you can get full scores in this question.

I suggest to use <font color=#bf2222>gate-level</font> description to do this question. (It may be much easy and stable.)

<img src="https://i.imgur.com/fG7YXID.jpg" style="zoom: 45%; display: block; margin: auto;" />

<font color=white>..</font>

module Flip_Flop (clk, d, q);
  input clk;
  input d;
  output q;
  wire n_clk;
  wire _q;
  not n1(n_clk, clk);
  Latch Master ( .clk (n_clk), .d (d), .q (_q) );
  Latch Slave  ( .clk (clk), .d (_q), .q (q) );
endmodule

module Latch (clk, d, q);
  input clk;
  input d;
  output q;
  wire not_d, not_q, a1, a2;

  not n1 (not_d, d);
  nand na1 (a1, d, clk);
  nand na2 (a2, not_d, clk);
  nand na3 (q, a1, not_q);
  nand na4 (not_q, a2, q);
 
endmodule

<font color=gray>Re-use the template from As4 part2.</font>

### Bonus

- You can submit Q3 again. However, you will get 80% points if you pass the testbench.
- <font color=#bf2222>Deadline: 5/24 </font>
- No point for late assignments.
- Please follow the description :)