Lab 3 Review
===
[TOC]

## Q1 Sequential Circuit

- Only use `<=` in DFF always blocks.

module q1(clk, rst, in1, in2, out1, out2);
    input clk, rst, in1, in2;
    output reg out1, out2;

    wire next_out1, next_out2;
    
    // DFF
    always@(posedge clk) begin
        if (!rst) begin
            out1 <= 1'b0;
            out2 <= 1'b0;
        end else begin
            out1 <= next_out1;
            out2 <= next_out2;
        end
    end
    
    // datapath
    assign next_out1 = in1 & in2;
    assign next_out2 = in1 | in2;


endmodule

## Q2 Fibonacci Sequence

module q2(clk, rst, f);
    input clk, rst;
    output reg [31:0] f;
    reg [31:0] fn_1;

    // DFF
    always@(posedge clk) begin
        if (!rst) begin
            f    <= 1'b1;
            fn_1 <= 1'b0;
        end else begin
            // hint: definition
            f    <= f + fn_1; 
            fn_1 <= f;
        end
    end

endmodule


## Q3 Separation of Computation from Sequential DFF Block

A DFF always block will be triggered only when the clock is rising. However, clock rising time is pretty short (maybe 1/1000 clock period). We can not expect that computation can be done in such short period. For example,

> Suppose that
> 1. clock period : 10ms
> 2. rising time : 0.001ms
> 3. computation time: 2ms
>
> The clock start rising on time `t` and we also start computation at the same time.
>
> clock finish rising : t + 0.001ms
> computation finish : t + 2ms
>
> During t + (2-0.001), the output is not correct, since the computation is not finished. So, an unexpected error occurs.

So, we usually do computation during the whole clock period and assign the value on posedge clock.

module q3(clk, rst, f);
    input clk, rst;
    output reg [31:0] f;
    
    reg  [31:0] fn_1;
    wire [31:0] next_f, next_fn_1;

    // DFF 
    always@(posedge clk) begin
        if (!rst) begin
            f    <= 32'b1;
            fn_1 <= 32'b0;
        end else begin
            f    <= next_f;
            fn_1 <= next_fn_1;
        end
    end
    
    // datapath
    assign next_f = f + fn_1;
    assign next_fn_1 = f;

endmodule

## Q4-1
By definition,
> Mealy circuit: sequential circuit for which the output is a function of both present state and input.
> Moore circuit: sequential circuit for which the output is a function of present state only.
>
> (letcure 5 Synchronous Sequential Logic p.37)

So, Q4-1 is a moore machine, since the output signal `out` is determined by the current state. (line 26 ~ 33)

module q4_1(clk, rst, in, out);
    input clk, rst, in;
    output reg [1:0] out;
    reg [1:0] state, next_state;
    
    // DFF
    always@(posedge clk) begin
        if (!rst) begin
            state <= `S0;
        end else begin
            state <= next_state;
        end
    end
    
    // datapath
    always@(*) begin
        case(state)
        `S0: next_state = (in) ? `S0 : `S1;
        `S1: next_state = (in) ? `S1 : `S2;
        `S2: next_state = (in) ? `S3 : `S0;
        `S3: next_state = (in) ? `S2 : `S0;
        endcase
    end

    // datapath
    always@(*)begin
    case(state)
        `S0: out = 2'd0;
        `S1: out = 2'd1;
        `S2: out = 2'd2;
        `S3: out = 2'd3;
        endcase
    end

endmodule

## Q4-2

此題送分

After re-considering, I think it is not a good example for explaining what is a mealy machine.

In a mealy machine, output signals change once the input signals change. <font color=gray>(e.g. Q5)</font>

<font color=#bf2222>However, in this question, `ans` will not change until the next clock cycle.</font>

To let Q4-2 be a mealy machine question, we can simply change the output singal `ans` to `next_ans`, since `next_ans` is determined by the current state and `in` (line 33 ~ 40).

module q4_2(clk, rst, in, out, ans);
    input clk, rst, in;
    output [1:0] out;
    output reg [31:0] ans;

    reg [1:0] state, next_state;
    reg [31:0]next_ans;

    // DFF
    always@(posedge clk) begin
        if (!rst) begin
            state <= `S0;
            ans   <= 32'd0;
        end else begin
            state <= next_state;
            ans   <= next_ans;
        end
    end
    // datapath
    always@(*) begin
        case(state)
        `S0: next_state = (in) ? `S0 : `S1;
        `S1: next_state = (in) ? `S1 : `S2;
        `S2: next_state = (in) ? `S3 : `S0;
        `S3: next_state = (in) ? `S2 : `S0;
        endcase
    end

    // datapath
    assign out = state;

    // datapath
    always@(*) begin
        case(state)
        `S0: next_ans = (in) ? ans - 32'd10 : ans + 32'd10;
        `S1: next_ans = (in) ? ans + 32'd88 : ans + 32'd87;
        `S2: next_ans = (in) ? 32'd5        : 32'd0;
        `S3: next_ans = (in) ? ans * 10     : ans * 5;
        endcase
    end

endmodule

## Q5 Sequence Detector

- Mealy Machine
- `out` will change its value once the input signal ,`in`, changes. (see the waveform)
- See the following sample code (line 28 ~ 35), we can find that `out` is determined by both `state` and `in`.


- State Trainsition
- The state transition diagram will be:

`define S0 2'd0
`define S1 2'd1
`define S2 2'd2
`define S3 2'd3

module q5(clk, rst, in, out);
    input clk, rst, in;
    output out;
    reg [1:0] state, next_state;
    reg out;
    
    always@(posedge clk) begin
        if (!rst) begin
            state <= `S0;
        end else begin
            state <= next_state;
        end
    end

    always@(*)begin
        case(state)
        `S0: next_state = (in == 1'b1) ? `S1 : `S0; 
        `S1: next_state = (in == 1'b1) ? `S2 : `S0; 
        `S2: next_state = (in == 1'b1) ? `S2 : `S3; 
        `S3: next_state = (in == 1'b1) ? `S1 : `S0; 
        endcase
    end
    always@(*)begin
        case(state)
        `S0: out = (in == 1'b1) ? 1'b0 : 1'b0;
        `S1: out = (in == 1'b1) ? 1'b0 : 1'b0;
        `S2: out = (in == 1'b1) ? 1'b0 : 1'b0;
        `S3: out = (in == 1'b1) ? 1'b1 : 1'b0;
        endcase
    end
    // alternative way
    // assign out = (state == `S3 && in == 1'b1) ? 1'b1 : 1'b0;

endmodule

## Q6 Sequence Detector 2
- State transition diagram (fig.1)

- code 1

...
assign z = (state == `S3 && a == b)? 1'b1 : 1'b0;
// z depends on state and a,b

- If Q6 is a moore machine, the state transition diagram will be: (fig.2)

- code 2

...
assign z == (state ==`S4) 1'b1 : 1'b0;
// z only depends on state.

- Comparing code 1 to code 2, it is very easy to know whether it is a mealy machine or a moore machine.
- code 1 : mealy
- code 2 : moore