• Review and Know-how
  • Randomization
    • Soft Constraints
    • Unique
  • Arrays
    • Slice an array element by a variable
  • OOP
    • super.super task call
    • paramters cannot be declare in a class
  • Package
  • Others
    • The Top Most Common SystemVerilog Constrained Random Gotchas
    • Chapters of Testplan
• Reviews from Google's stuff on 2022
  • DV methodology
  • SystemVerilog Class
    • 1: Basics
    • 2: Static Members
    • 3: Aggregate Classes
    • 4: Inheritance
    • 5: Polymorphism
    • 6: Virtual Methods and Classes
    • 7 Randomization
    • 8 Constraints
  • Verification Guide

Review and Know-how

Randomization

Soft Constraints

• Soft constraints are default constraints which hold true until contradicted by another similar constraint.

  Ref.: http://vlsiwithvikas.blogspot.tw/2016/05/system-verilog-soft-constraints.html

Unique

unique { open_range_list- }

• References:
  • SystemVerilog Unique Constraint
• can only be used on numeric variable
  • From 18.5.5 in IEEE 1800-2017:
    The open_range_list in a uniqueness_constraint shall contain only expressions that denote scalar or array variables

Arrays

Slice an array element by a variable

// TODO

OOP

super.super task call

• How to traverse all the members of an enumeration

  Reference IEEE Std 1800-2017 6.19.5 Enumerated type methods

paramters cannot be declare in a class

• An Example:

  ​​class ec_ctl_mem_lock_reg0_sequence extends ec_ctl_base_sequence;
  ​​parameter ec_addr_width   = ec_cfg.ec_addr_width;
  

  will get a compiling error

  ​​​​Error-[SV-IRTAV] Illegal reference to automatic variable
  ​​​​../../../../vsrc/ec_tb/ec_ctl_base_sequence.sv, 1518
  ​​​​"ec_cfg.ec_addr_width"
  ​​​​  Hierarchical reference to automatic variable 'ec_addr_width' is not legal.
  ​​​​  Declared at:
  ​​​​  "../../../../vsrc/ec_tb/ec_config.sv", 439
  

  From the section 5.3 constant of SV 3.1a LRM:

  A parameter or local parameter can only be set to an expression of literals, parameters or local parameters, genvars, enumerated names, or a constant function of these. Hierarchical names are not allowed.

  –> Hierarchical names are not allowed

  Get the other error:

  ​​Error-[NCE] Non-constant expression
  ​​The following expression should be a constant.
  ​​Expression: (64 - this.ec_addr_width)
  ​​"../../../../vsrc/ec_tb/ec_ctl_base_sequence.sv", 1543
  ​​Source info:     wr_data[0][63 -: (64-ec_addr_width)] = 
  ​​'{(64-ec_addr_width){'b1}};//reserved and read as all 1. So initialising to 
  ​​all 1
  ​​'this' is not an elaboration-time constant. To correct the error you may 
  ​​convert this const variable to a parameter or a localparam.
  

Package

Others

The Top Most Common SystemVerilog Constrained Random Gotchas

• https://dvcon-europe.org/sites/dvcon-europe.org/files/archive/2014/proceedings/T5_1_paper.pdf

Chapters of Testplan

1. HW SPEC study
   • list features
2. List direct tests for each feature
   • Completion criteria: mini/full regressions all pass
     • Code freeze for back-end synthesis
3. Do random tests and collect coverages
   • extend direct tests to random tests
     • Completion criteria: random regressions all pass for weeks
     • if a bug is found, designer does ECO to fix the bug and verifier create a direct test for testing the fixed design
   • collect line/fsm/toggle/functional/assertion coverages
     • Completion criteria: at least line and fsm coverages achieve 100%
4. Chip tape out and prepare cases to bring chip up
   • run random tests until chip is produced

Reviews from Google's stuff on 2022

Items related to DV in Helpful links and videos to prepare for the interview process:

DV methodology

which takes many forms, including test planning, coverage methodology, test bench methodology, etc

SystemVerilog Class

1: Basics

• Class Overview
  A class is a user-defined data type

  • Must be delcared in a module, package, or interface
  • it cannot be compiled standalone

  Class object
  can be dynamically created and deleted during simulation

  • (Review) malloc/free an object on 11.26 Memory management in < SV 3.1a LRM >

  Used in Object-Oriented (OO) programming for testbenches and simulation models

  • Abstract data modeling
  • Inheritance
  • Data hiding and encapsulation
  • Polymorphism
    • TO-REVIEW

• Variables of the Class Type
  

  A variable of a class type is called a handle

  • Uninitialized value is null

  A class instance must be created for handle using a constructor, new function

  • Creates an area of memory holding the class instance
  • Assigns the memory pointer to the handle

  An instance persists until it is no longer in use

  • No deconstructor
  • Automatic "garbage collection" like C++

• Class Properties and Methods
  The class type declaration declares class members:

  • Data items, called properties or fields
  • Tasks or functions which operate on data items, call methods

• External Method Declaration
  

• Class Example

  • Practice
    Module info
    

    My answer:

2: Static Members

• Can only access static properties or other static methods
  • 建議透過 class 的名子加上resolution operator :: 來存取 static 變數

    可以清楚的表示該 member 是靜態的

• practice

3: Aggregate Classes

• Properties of a Class Type
  

  
  • A class property can be an instance of another class
    e.g. the class frame handles f1 and f2 in the class twoframe
  • 必須明確地呼叫 class properties 的 constructors

• Encapsulation and Aggregate Classes
  
  
• Aggregation Summary
  
  

4: Inheritance

• subclass 可以 re-declare (over-ride) parent members
  
  $\to$ 透過宣告相同名字的task或function
• The keryword super
  

  • parent 的 constructor 會自動被 subclass 的 constructor 執行

    • 可以想像是subclass constructor 的第一行
    • 即 parent 的 new() 放到 subclass 的 new() 中

  • 但上例在 construct subclass badtagframe 時會遇到 "compilation error"
    • 因為 implictly 呼叫 parent 的 new()，沒有給予需要的引數(arguments)
      
      
      
      $\to$ 明確地呼叫 parent 的 new()，by super keyword，並給予其需要的引數
• 在多層的繼承，subclasses 的建構子 (constructors)，必須明確地將引數往需要的 class 傳
  
  • 一次只能傳一層, 故不能寫以下的 code
    ​​​​super.super.new()
    

5: Polymorphism

• Multiple subclasses

  • 當我們需要基底類型的成員(member)有不同的 (?)值 的一個子類別(subclass)，此時會宣告多個繼承基底類型的子類別並給予他們成員不同的值；以不同的 constraints 為例:
    • Source code
      
    • Relation of the classes
      

      每個子類型只有一個 parent

  • C++的多重繼承

• Polymorphism的需求

  • 延續上例；當我們有不同種類的frames，要如何存取他們？

    1. 每種frame都宣告一個handle
       

       $\to$ 需要多個記憶體空間來儲存handles

    2. 不同子類別的實例(instance)可以共用一個handle

       The OOP term for multiple methods sharing a common name is “polymorphism.”

       提供一個 virtual method 供上層 programmer 參考，以簡化 coding 的思考；而此 method 可能有不同種類的實作，這部份可以交由底層的 programmer 來攥寫

  • 所以一個handle type 的概念:
    • Class type is used in declaration and the contents of the handle
    • Class instance is held by the handle
      

• 實例：Assigning Subclass/Parent Instance to Parent/Subclass Handle

  ​​handle of parent = handle of subclass // 允許
  ​​handle of subclass = handle of parent // 會有編譯上的錯誤 
  

  觀念是？

  • subclass 有包含 parent 所有的 propertities , 所以 subclass 的 handle 可以無痛 copy 給 parent 的 handle；如下例 BadTr 繼承 Transaction:
    

    承上，一個 Cast base class 的 handle 到 指向一個由此 base type 延伸出來的 class 的 object 的動作，稱作 Downcasting 或 conversion

  • 反之, parent 沒有包含 subclass 所有的 propertities，所以無法將指向自己的 handle copy 給 subclass 的 handle
    

    • parent 不能存取 child 的成員
    • 但，並非全然不行；只是必須先使用$cast。
      • 若 base handle 原來是指向一個 extened object，則此賦值是允許的
      • 所以賦值前需先透過 $cast 來檢查上述條件；記住，這裡是檢查物件的型別，並非只是 handle。如以下範例：
        

    A know-how:

    • 建議在做 base/extended classes 與 base/extended handle 的賦值前，都加上 $cast, 以確保型別是相容的(compatible)
    • Sample 8.14 中，最後透過將 $cast 當作 函數 呼叫 (結果是透過回傳值，不會有 simulation error) 的部份，可改寫成
      • macro, 如 Section 6.3.2 的 SV_RAND_CHECK macro
      • 不要使用 immediate assert statement 當作此 assertion expression 使用；若 assertions 被關掉，此 statement 就不會被 evaluated

  References

  • 8.3.1 Downcasting with $cast in
    < SystemVerilog for Verifiction, 3rd >
  • 11.13 Overridden members

• 實例：一個包含不同種類 frame 的 array
  

6: Virtual Methods and Classes

• multi-level inheritance

  • class member access is restricted

    Class members are resolved by searching from class handle type

    
    
    parent 不能存取 child 的成員 in 5-Polymorphism
    –> could use $cast system task introduced on the above section; but there's an easier solution…

• the above restriction can be resolved by Virtual methods

  Virtual methods are resolved according to the contents of a handle, NOT the type of the handle

• class method resolution
  • which class method will be referenced
    

• virtual class and pure virtual method
  

• 延伸閱讀： 11.17 Data hiding and encapsulation in LRM
  Here raise a question:

  Does SystemVerilog have the reserved words like “public” and “private” which are in C++?
  • A: Yes. But some of names of the reserved words are different:
    • Public → ___ (needs no reserve word);
      in SV, unqualified class properties and methods are public, available to anyone who has access to the object’s name.
    • Private → local;
      we don't want some members to be accessible from outside. Further, they are also not visible within subclasses
    • Protected → protected;
      in case we want the local members to be accessible to a child.
      A protected class property or method has all of the characteristics of a local member, except that it can be inherited; it's visible to subclasses

7 Randomization

Random Class Properties

• rand: random with ++uniform distribution==
• randc: random-cyclic randomly iterates through all values without repetition
  
  

8 Constraints

• Constraint Expressions: Set Membership
  
  
  by the inside operator:
  ​​[!] (expression) inside { set })
  

• Constraint Expressions: Weighted Distributions
  
  

  reference note on 12.4.4 Distribution in SV 3.1a LRM

Verification Guide

Review the following items in SystemVerilog-for-Verification-3rd-by-Chris-Spear-and-Greg-Tumbush

• Arrays
  • Chapter 2 Data Type in <SystemVerilog for Verification (3rd)>
    • Choosing a Storage Type
• Processes
  • Chapter-7-Threads-and-Interprocess-Communication
• Tasks and Functions