# Prepare interview for Google DV
## Information from recruiter
### Role Overview
**We are looking for the following skill sets:**
#### Design Verification (Simulation) Roles:
- DV methodology (which takes many forms, including test planning, coverage methodology, test bench methodology, etc)
- SV and SV-TB semantics and coding (This includes many things - OOP, SV constraint coding, modeling, coverage coding, SVA if appropriate)
- UVM methodology and UVM coding

### Preparing for Interviews
- Focus on what you know. The team appreciates proactivity and curiosity. Besides your technical approach in the interview, you can expect to be asked about your interest in the role and business area, your experiences, why you want to work for Google and why we should hire you.

#### Remember, at Google we are looking for people who:
- Thrive in small, focused teams and high-energy environments
- Are well-rounded with diverse interests and skills
- Believe in the ability of technology to change the world
- Are as passionate about their lives as they are about their work
- Have excellent communication and organizational skills
- Are enthusiastic, self-motivated and team-players
- Have broad knowledge and expertise in many different areas

#### :star: Helpful links and videos to prepare for the interview process:
**Items dedicated to Google**
- [x] [Google Hardware](https://www.youtube.com/watch?v=s1goXirGE5U&index=2&list=PLFECEBD167E54B802&t=0s)
- [x] [Meet Hardware Engineers at Google](https://www.youtube.com/watch?v=OdmSXXfknU8&list=PLllx_3tLoo4fd1deqnzvyZrIrJzRdSC6-)
- [x] [About Google](https://about.google/intl/en/)
- [x] [How Google Hires](https://www.youtube.com/watch?v=k-baHBzWe4k&list=PLllx_3tLoo4c_aR8RKOOnizL5LiUH02YF)
- myth-busting: 神話破滅
- brain teaser: 腦筋急轉彎

##### :star: **Items related to prepare interviews**

- [ ] [How to Prepare for a Technical Interview at Google](https://www.youtube.com/watch?v=ko-KkSmp-Lk&index=2&list=PLllx_3tLoo4c_aR8RKOOnizL5LiUH02YF)
- [ ] [Sample Coding Interview (This is for software, but Hardware candidates can reference)](https://www.youtube.com/watch?v=XKu_SEDAykw)

##### :star: **Items related to DV**
- [x] [SystemVerilog Classes (Important)](https://www.youtube.com/playlist?list=PLYdInKVfi0KZ1HMVNNcxvvWhYJMmLAq_g)
Focus on:
- [x] **OOP**: figure out which class members and functions are invoked based on the different handle type vs. instance type
- [x] **Randomization**: how to construct a class that supports randomization; how to invoke and control randomization
- [x] **Constrained randomization**: be familiar with the constraint syntax, and practice constraint coding
- [ ] [Verification Guide](https://verificationguide.com/systemverilog/systemverilog-tutorial/)
Focus on:
- [x] Data Types
- [x] Arrays: understand the differences in array types including space/time efficiency; practice coding some complex data structures using these array types. ==Many easy-to-medium diculty data structure problems on LeetCode can also be solved using SV==.
- [x] Queue
- [x] Processes
- [ ] Tasks and Functions
- [ ] [UVM Tutorial](https://verificationguide.com/uvm/uvm-tutorial/)
Focus on:
- [ ] TB hierarchy
- [ ] Sequence vs. sequencer
- [ ] How TLM works
- [ ] How phases work
- [ ] Try to code some simple agents (driver or monitor) based on protocols you’re familiar with.
- [ ] [SystemVerilog Tutorial](https://www.chipverify.com/systemverilog/systemverilog-tutorial)
- [ ] [UVM User Guide](https://www.accellera.org/images/downloads/standards/uvm/uvm_users_guide_1.2.pdf)
- [ ] [SystemVerilog LRM](https://ieeexplore.ieee.org/document/6469140?reload=true)
- [ ] Our head of DV, Jon Michelson, has authored a few books and holds a few patents for DV. If you have the time, we recommend looking into those! Here’s a good article to start with: [Practical Approaches to Deployment of SystemVerilog Assertions](https://www.edn.com/practical-approaches-to-deployment-of-systemverilog-assertions/)

#### Interview Tips
- Listen to everything the interviewer says as he/she may be trying to give you hints or steer you in another direction.
- If you don’t understand the questions, ask for clarication. Don’t guess or assume. The interviewer is there to help if you need it.
- Approach a large problem by taking it apa into small pieces and describe how you would like to tackle solving each pa of the question. The interviewer is as interested in how you approach problems as whether you reach the intended result.
- Don't give up on problems - ask the interviewer for advice.
- THINK OUT LOUD - talk through your decision-making process and technical skills. We are looking for technical talent, but also people who can explain their thought process and analytically describe how they come up with their answers.
- Be prepared to justify your answers with solid reasoning or come up with alternative solutions if something does not work.
- Ask questions to show you are interested and are analytical, showing that you are thinking about the role, the question, the problem, etc. Prepare some questions for the interviewer - how does he/she structure their day? What products have they enjoyed working on? Etc.
- Don't worry if your interview is tough - engineers want to stretch you to see what you know and how you deal with new information.

### Technical Preparation
We recommend going through the job description and being prepared to answer questions about any skills listed in both the minimum and preferred qualifications.

#### In addition, you’ll be tested on your specific skills, which could include any of the following:
- [ ] in General: OOP, coverage and SV constraints
- [ ] Verification methodology
- [ ] Testbench coding
- [ ] SystemVerilog (synthesizable and testbench) coding
- [ ] UVM methodology and coding
- [ ] Assertion methodology (if applicable)
- [ ] SVA (SystemVerilog Assertions) coding (for formal verification role only)
- [ ] Perl and Python scripting (if applicable)
- [ ] Formal verification methodology and techniques (for formal verification role only)

Types of technical questions:
- Problem Solving questions - Might require using the whiteboard and talking through solutions or scenarios routed within Verification.
- Academic questions - Similar to questions you may have gotten on an exam in college. We strongly recommend studying up on the digital systems and digital logic that are prevalent in the industry, fundamental algorithms, and industry-specific acronyms.
- Technical Coding questions - Usually in SystemVerilog and UVM. Other verification languages and UVM-like methodologies are also accepted, depending on your experience.

What to Expect - Technical Phone (or Google Hangout) Interview
- This interview will be conducted via phone or Google Hangouts and will require you to have access to a computer and internet. You will be required to write and share code by using Google Docs to code in real time. If you have never written code on Google docs before, we suggest practicing prior to the interview.
- The interviewer will usually start off with one or two questions about your career and past experiences, but the majority of the interview will focus on technical coding questions. The interview will be about 45 minutes.
- You WILL be required to code, usually in SystemVerilog, but other verification languages are also acceptable depending on your past experience. Please ensure that the proper methodology is followed. Your code should have no syntax errors and solve the problems asked.

Some chips made by Google:
https://www.webmproject.org/hardware/vp9/bige/
https://www.blog.google/products/pixel/pixel-visual-core-image-processing-and-machine-learning-pixel-2/
https://cloud.google.com/blog/products/gcp/titan-in-depth-security-in-plaintext
https://developers.googleblog.com/2018/07/new-aiy-edge-tpu-boards.html

## Meeting with recruiter
### 04/28/2021
- 最近有新成立的CPU Team, 雖然目前Manager想找有經驗的，不過還是可以先投投看履歷，職缺內容如下：
https://careers.google.com/jobs/results/103455667181757126-cpu-design-verification-and-emulation-engineer/
- 面試流程
1. 詢問SV/UVM/OOP concept in *15* min
2. Verifiation flow on a DUT in *15* min
3. Coding on UVM/SV in *20~30* min
- constraint randomization
- 刷leecode練習OOP
- 因為時間有限，可以邊coding邊講concept
- [x] 可以先準備resume
### 04/07/2022
**與interviewer約interview的日期與時間**
- Interviewer: CPU DV technical lead
- 日期: 台灣禮拜二到禮拜六, 時間：美國時間
- 考試項目
- CPU arch/logic design
- Verification methodology
- Programming: SystemVerilog/C
- 用google doc
### h3
- 面試日期：5/19
### 04/28
- CPU相關職缺已額滿，通知面試取消
### 05/01
- Recruiter詢問是否要嘗試另一個DV的職缺
:spiral_note_pad: 回覆如下：

  Hi Wendy:
  
  不好意思，前天下午因緊接著打工，所以沒有立即回覆您；剛好也思考了一下是否要立即apply ASIC DV的職缺。有關這部份，小的思考過後，目前還是會以找CPU architect或相關的職缺為主，也有同步在看其他有開類似職缺的公司。不過個人還是蠻喜歡Google的工作環境跟氣氛的，如果有機會還是蠻想加入的；請問我可以之後再來apply ASIC DV的職缺嗎？

  真的很謝謝您幫忙小的這麼多。

### 09/07 call with recruiter
- Google目前招募減緩，面試期間可能需要**兩個月**

## Items to prepare
### for CPU DV engineer
:information_source: study principle: 透過課程及題目檢視自己不足的部份，並立即補上；而非只做題目，不求甚解。
- Computer architecture
- week6 to week13: 8 weeks needed
一個禮拜看兩週的課程, 需要4個禮拜
- 資訊科技公司面試演練
- not sure about studying to which week
- Linux kernel
- week1 to week4
- DV review / stuff on resume
- one~two weeks

:::info
Expect to schedule interview on the from 5/16 to 5/23
:::

# References
## Current events relate to Google
- [Google I/O 2021: Everything announced at the keynote](/FqyIuSeUQRaNVapCkP5N_w)

###### tags: `Digital_Verification` `career` `google`