owned this note
owned this note
Published
Linked with GitHub
---
title: SystemVerilog 3.1a Language Reference Manual
tags: system-verilog
---
:spiral_note_pad: [The manual with my markers](https://drive.google.com/open?id=0B4Iyj3yMR1idVWo5UVdaODhUcms&resourcekey=0-4El-HEjGn91VfECHZQa6wQ&authuser=kchs.tw%40gmail.com&usp=drive_fs)
[TOC]
# Section 3 Data types
## 3.15 $cast dynamic casting
:star: It’s important to note that $cast performs a run-time check. **No type checking** is done by the compiler, except to check that the destination variable and source expression are singulars.
:::info
結論優先
Allowing both types of casts gives full control to the user. If users know that it is safe to assign certain expressions to an enumerated variable, **the faster static compile-time cast can be used**. If users need to check if the expression lies within the enumeration values, it is not necessary to write a lengthy switch statement manually,the compiler automatically provides that functionality via the $cast function. By allowing both types of casts,
==users can control the time/safety trade-offs.==
:::
# Section 11 Classes
## 11.1 Introduction (informative)
- SystemVerilog introduces an object-oriented `class` *data abstraction*.
- `Classes` allow objects to be dynamically created, deleted, assigned, and accessed via `object handles`.
- `Object handles` provide ++a safe pointer-like mechanism++ to the language.
- `Classes` offer ++inheritance and abstract type modeling++, which brings **the advantages of C function pointers** with *none of the type-safety problems*
- Bringing *true polymorphism into Verilog*
## 11.4 Objects (class)
A class defines a data type. An object is an instance of that class. An object is used by first declaring a variable
of that class type (that holds an object handle) and then creating an object of that class (using the new function)
and assigning it to the variable.
```verilog
Packet p; // declare a variable of class Packet
p = new; // initialize variable to a new allocated object of the class Packet
```
- The *variable* `p` is said to ++hold an object handle++ to *an object of class Packet*.
:notes: SystemVerilog objects are referenced using an $object\ handle$. There are some differences between a C pointer and a SystemVerilog object handle.
- *A C pointer can be incremented* for example, but a SystemVerilog object handle cannot.
> 延伸閱讀: In addition to object handles, Section 3.6 introduces the `chandle` data type for ==use with the DPI Direct Programming Interface== (see Section 27).
## 11.11 Assignment re-naming and copying
Declaring a *class variable*, only creates the name by which the object is known. Thus:
> 宣告一個 *class variable*, 只會建立欲建構(construct) 物件(object) 的名字；如下敘述式的`p1` [color=blue]
```verilog
Packet p1;
```
`p1`, 可以握著 class `Packet` 的 物件 的 handle (把手)
> reference [114-Objects-class](https://hackmd.io/VcksXsrUTsK5IGEnn2xFjg?both#114-Objects-class) for clarification
### Shallow copy
:goal_net: to Make a copy of `p1`
```verilog
Packet p1;
Packet p2;
p1 = new;
p2 = new p1;
```
- The last statement has new executing a second time, ++thus creating a new object p2++, ==whose class properties are copied from p1==.
- :notes: This is known as a *shallow copy*
- ++All of the variables are copied across++: integers, strings, *instance handles*, etc. *Objects*, ==however, are not copied, only their handles==;
如以下 [Aggregate Classes](https://hackmd.io/mSdqwKkLSfCIM_GWfhCwOQ#3-Aggregate-Classes) 的範例
```verilog=
class A ;
integer j = 5;
endclass
class B ;
integer i = 1;
A a = new;
endclass
function integer test;
B b1 = new; // Create an object of class B
B b2 = new b1; // Create an object that is a copy of b1
b2.i = 10; // i is changed in b2, but not in b1
b2.a.j = 50; // change a.j, shared by both b1 and b2
test = b1.i; // test is set to 1 (b1.i has not changed)
test = b1.a.j; // test is set to 50 (a.j has changed)
endfunction
```
:::info
於上述程式碼：
++line 12++: `b2` 指向一個 b1 copy 的 object
++line 14跟16++: Object `a` 是被 `b1` 和 `b2` share 的，不會因為有 `instantiation opertion` **new**, 就再建構一個 object
可以總結以下幾點：
1. class properties and instantiated objects can be initialized directly in aclass declaration.
> 如上例的 ++line 6-7++ 所示
2. the shallow copy does not copy objects.
> 如上例的 ++line 14-16++ 所示
3. `instance qualifications` ++can be chained++ ==as needed to reach into objects== or ==to reach through objects==；如下例:
```verilog
b1.a.j // reaches into a, which is a property of b1
p.next.next.next.val // chain through a sequence of handles to get to val
```
:::
### full (deep) copy
:notes: by `copy` method
```verilog
Packet p1 = new;
Packet p2 = new;
p2.copy(p1);
```
where `copy(Packet p)` is ++a custom method++ written to copy the object specified as its argument into its
instance.
## 11.12 Inheritance and subclasses
- ==The parent’s methods can also be overridden==, changing their definitions.
- ==The mechanism provided by SystemVerilog is called Single-Inheritance==, that is, ++each class is derived from a single parent class++.
## 11.13 Overridden members
參考[此章節範例的原始碼](https://www.edaplayground.com/x/Vr6N)
由此範例可以觀察到以下幾點：
* 因為 subclass objects 是 parent classes 合法表示的objects (legal representative objects)，所以 subclass (LinkedPacket) 的 handle 可以指派給 parent class (Packet)
* 從 parent handle `p`, subclass (LinkedPacket) 的 ==new 及 所有overridden的成員都是被隱藏的==
* 從結果的*第一個* $display 可觀察到
* 若要從 parent class object (`p` in the example) 呼叫 overridden method, 此 method 需要被宣告成 **virtual** (see Section 11.19)
* 從結果的*第二個* $display 可觀察到
## 11.26 Memory management
When an object is no longer needed, ==SystemVerilog automatically reclaims the memory==, making it available for re-use
- :notes: How to free an object manually?
Assign null to the handle of the object.
- Similarly, when an object goes *out of scope*, the system ==implicitly assigns **null** to the object==.
# Section 12 Random Constraints
## 12.4 Constraint blocks
### 12.4.4 Distribution
:notes: The distribution operator **dist** evaluates to true if the value of the expression is contained in the set; otherwise it evaluates to false.
Optionally, each term in the
list can have a weight, which is specified using the `:=` or `:/` operators. ++If no weight is specified for an item, the default weight is := 1++
- The := operator assigns the specified weight to the item, or if the item is a range, to every value in the range.
- The :/ operator assigns the specified weight to the item, or if the item is a range, to the range as a whole. If there are n values in the range, the weight of each value is range_weight / n.
For example:
```verilog
x dist {100 := 1, 200 := 2, 300 := 5}
```
- means x is equal to 100, 200, or 300 with weighted ratio of 1-2-5.
:notes: It is easier to think about *mixing ratios*, such as 1-2-5, than the actual probabilities because mixing ratios ++do not have to be normalized to 100%++.
- Converting probabilities to mixing ratios is straightforward.
When weights are applied to ranges,
they can be applied to each value in the range, or they can be applied to the range as a whole. For example,
```verilog
x dist { [100:102] := 1, 200 := 2, 300 := 5}
```
- means `x` is equal to 100, 102, 200, or 300 with a weighted ratio of 1-1-1-2-5.
```verilog
x dist { [100:102] :/ 1, 200 := 2, 300 := 5}
```
- means `x` is equal to 100, 102, 200, or 300 with a weighted ratio of 1/3-1/3-1/3-2-5.
:notes: In general, distributions guarantee two properties: set membership and *monotonic weighting*,
- which means that increasing a weight increases the likelihood of choosing those values.
Limitations:
- :notes: A dist operation shall not be applied to ++randc++ variables.
- A dist expression requires that expression contain at least one rand variable.
# Section 16 Program Block
## 16.1 Introduction (informative)
The `module` is the basic building block in Verilog.
- Modules can contain hierarchies of other modules, wires, task and function declarations, and procedural statements within always and initial blocks.
- This construct works extremely well for the description of hardware.
However, ++for the testbench++, the emphasis *is not* in the hardware-level details such as wires, structural hierarchy, and interconnects,
- but in modeling the complete environment in which a design is verified
A lot of effort is spent getting the environment:
- properly initialized and synchronized,
- avoiding races between the design and the testbench,
- automating the generation of input stimuli,
- and reusing existing models and other infrastructure.
The program block serves three basic purposes:
1. It provides +=an entry point to the execution of testbenches++.
2. It creates a scope that encapsulates program-wide data.
3. It provides ==a syntactic context that specifies scheduling in the Reactive region==
The program construct serves as a clear separator between design and testbench, and, more importantly
- it specifies ++specialized execution semantics++ in the *Reactive region* for all elements declared within the program.
## 16.2 The program construct
`Type and data declarations` within the program are *local to the program scope* and ++have static lifetime++.
`Program variables` can only be assigned using *blocking assignments*.
## 16.3 Multiple programs
The programs can be fully independent (without inter-program communication), or cooperative.
The degree of communication can be controlled by choosing to share data using nested blocks, packages, or hierarchical references, or making the data
private by declaring it inside the corresponding program block.
- [ ] examples
- `import package::*;`
- ...
## 16.4 Eliminating testbench races
Google Drive
Gist
Clipboard
Sign in with Wallet
