Computer Architecture 2021 Fall Assignment3

contrubuted by < oucs638 >

Environment Setup

Follow Lab 3 step install srv32.
Follow TA's setup tutorial.

Install gtkwave.



# Install gtkwave using apt-get on ubuntu 20.04
sudo apt-get update
sudo apt-get -y install gtkwave

Start

Requirement 1

Create directory in srv32/sw and create my c code and Makefile (copy from the Makefile in other directory in srv32/sw).







# In srv32/sw/
mkdir tribonacci
cd tribonacci
# Put my code in assignment1
vim tribonacci.c
# Copy Makefile and modify "SRC" and "TARGET"
cp ../hello/Makefile ./

C code





























#include <stdio.h>

int tribonacci(volatile int n)
{
    int t0 = 0, t1 = 1, t2 = 1, t3 = 0;

    if (n == 0)
        return 0;
    else if (n == 1 || n == 2)
        return 1;

    for (int i = 2; i < n; i++) {
        t3 = t0 + t1 + t2;
        t0 = t1;
        t1 = t2;
        t2 = t3;
    }

    return t3;
}

int main(void)
{
    volatile int num = 10;
    volatile int ans = tribonacci(num);
    printf("The result is %d.\n", ans);

    return 0;
}

Back to srv32 and run tribonacci.



# In srv32 
make all
make tribonacci

Running results












































make[1]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw'
make -C common
make[2]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/common'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/common'
make[2]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/tribonacci'
riscv-none-embed-gcc -O3 -Wall -march=rv32im -mabi=ilp32 -nostartfiles -nostdlib -L../common -o tribonacci.elf tribonacci.c -lc -lm -lgcc -lsys -T ../common/default.ld
riscv-none-embed-objcopy -j .text -O binary tribonacci.elf imem.bin
riscv-none-embed-objcopy -j .data -O binary tribonacci.elf dmem.bin
riscv-none-embed-objcopy -O binary tribonacci.elf memory.bin
riscv-none-embed-objdump -d tribonacci.elf > tribonacci.dis
riscv-none-embed-readelf -a tribonacci.elf > tribonacci.symbol
make[2]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/tribonacci'
make[1]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw'
make[1]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sim'
The result of tribonacci(10) is 149.

Excuting 2847 instructions, 3689 cycles, 1.295 CPI
Program terminate
- ../rtl/../testbench/testbench.v:418: Verilog $finish

Simulation statistics
=====================
Simulation time  : 0.094 s
Simulation cycles: 3700
Simulation speed : 0.0393617 MHz

make[1]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sim'
make[1]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/tools'
./rvsim --memsize 128 -l trace.log ../sw/tribonacci/tribonacci.elf
The result of tribonacci(10) is 149.

Excuting 2847 instructions, 3689 cycles, 1.296 CPI
Program terminate

Simulation statistics
=====================
Simulation time  : 0.003 s
Simulation cycles: 3689
Simulation speed : 1.240 MHz

make[1]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/tools'
Compare the trace between RTL and ISS simulator
=== Simulation passed ===

Requirement 2

Read the signals inside srv32 associated to PC, branch, instruction memory (I-MEM), data memory (D-MEM), and instruction internals.

Requirement 3

Remove the function and volatile to optimize.
Create new directory in srv32/sw named tribonacci_opt.

Put new C code in tribonacci_opt and back to srv32/, then run make tribonacci_opt.

New C code























#include <stdio.h>

int main(void)
{
    int num = 10, ans = 0;

    if (num == 1 || num == 2)
        ans = 1;
    else {
        int t0 = 0, t1 = 1, t2 = 1;

        for (int i = 2; i < num; i++) {
            ans = t0 + t1 + t2;
            t0 = t1;
            t1 = t2;
            t2 = ans;
        }
    }

    printf("The result of tribonacci(%d) is %d.\n", num, ans);

    return 0;
}

Running result













































make[1]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw'
make -C common
make[2]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/common'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/common'
make[2]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/tribonacci_opt'
riscv-none-embed-gcc -O3 -Wall -march=rv32im -mabi=ilp32 -nostartfiles -nostdlib -L../common -o tribonacci_opt.elf tribonacci_opt.c -lc -lm -lgcc -lsys -T ../common/default.ld
riscv-none-embed-objcopy -j .text -O binary tribonacci_opt.elf imem.bin
riscv-none-embed-objcopy -j .data -O binary tribonacci_opt.elf dmem.bin
riscv-none-embed-objcopy -O binary tribonacci_opt.elf memory.bin
riscv-none-embed-objdump -d tribonacci_opt.elf > tribonacci_opt.dis
riscv-none-embed-readelf -a tribonacci_opt.elf > tribonacci_opt.symbol
make[2]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw/tribonacci_opt'
make[1]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sw'
make[1]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sim'
The result of tribonacci(10) is 149.

Excuting 2776 instructions, 3604 cycles, 1.298 CPI
Program terminate
- ../rtl/../testbench/testbench.v:418: Verilog $finish

Simulation statistics
=====================
Simulation time  : 0.068 s
Simulation cycles: 3615
Simulation speed : 0.0531618 MHz

make[1]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/sim'
make[1]: Entering directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/tools'
./rvsim --memsize 128 -l trace.log ../sw/tribonacci_opt/tribonacci_opt.elf
The result of tribonacci(10) is 149.

Excuting 2776 instructions, 3604 cycles, 1.298 CPI
Program terminate

Simulation statistics
=====================
Simulation time  : 0.005 s
Simulation cycles: 3604
Simulation speed : 0.729 MHz

make[1]: Leaving directory '/home/oucs638/GitHub/CA_2021_FALL/Assignment3/srv32/tools'
Compare the trace between RTL and ISS simulator
=== Simulation passed ===

Differences before and after optimization





















> Before optimization:

Excuting 2847 instructions, 3689 cycles, 1.296 CPI
Program terminate

Simulation statistics
=====================
Simulation time  : 0.003 s
Simulation cycles: 3689
Simulation speed : 1.240 MHz

> After optimization:

Excuting 2776 instructions, 3604 cycles, 1.298 CPI
Program terminate

Simulation statistics
=====================
Simulation time  : 0.005 s
Simulation cycles: 3604
Simulation speed : 0.729 MHz