Assignment3: SoftCPU

Due: Dec 20, 2021

Requirements

Following the instructions of srv32 - RISCV RV32IM Soft CPU, you shall modify the assembly programs used/done with Assignment1 for srv32 Simulation with Verilator.
- dhrystone is a good starting point for writing test cases.
- You should validate the results in your program(s).
- You should program in RISC-V assembly for the sake of further optimizations. Hint: You may modify a customized Makefile for building C and assembly source files from scratch.
Check the generated file wave.fst and use GTKwave to view the waveform. Then, explain how your program is executed along with srv32 Simulation.
- Show the signals/events inside srv32 associated to PC, branch, instruction memory (I-MEM), data memory (D-MEM), and instruction internals.
- You shall discuss pipeline architecture along with your program.
Propose the software optimizations (against your program) based on the pipeline design of srv32.
- fewer instructions
- shorter cycle counts
- eliminate unnecessary stalls
Write down your thoughts and progress in HackMD notes.
- Summarize how RISC-V Compliance Tests works and why the signature should be matched.
- Explain how srv32 works with Verilator.
- BONUS: Can you figure out the room to improve srv32?