Programming FPGA on USRP 2944R/Ettus X310 with UHD & RFNoc – I

Starting with 1In1Out RFNoC Module

For mutiple I/O realization, please take the following link. There are more details about the whole system as well.

• Programming FPGA on USRP 2944R/Ettus X310 with UHD & RFNoc – II
• Problem Collection for USRP

Preliminary

This project is going to migrate DSP based on Verilog onto NI-USRP 2944R. Since the development tool is different from vivado, which I'm more familiar with. Hoping this starting guide can help any newer to USRP.

Introduction

Since there are UHD3.0 & UHD4.0 already, as well as RFNoC3.0 & RFNoC4.0. All of them are still under-maintained but there isn’t downward compatibility. Actually, the tools are quite different for them. That leads to the workflow differently. For me, I follow the starting guide, the instruction let me git clone the RFNoC4.0, while the guides are written for the RFNoC3.0. Besides, RFNoC4.0 has just been introduced for over a year. Most of the resources are based on 3.0. The document for starting RFNoC4.0 is not clear about its dependency though.

Thus after a week of debugging, I summarized the workflow so far from my own experience. I'm still improving this project and the note. Please feel free to contact me or leave a message.

0. Some points that we should be caution

• UHD is the usrp driver.
• RFNoc is in gr-ettus package. It wraps the custom FPGA block (or IP).
• GNU radio is the GPP radio software.

UHD4.0 works with RFNoc4.0, GNU radio3.8, Xilinx Vivado 2019.1. Make sure each version is capable to each other, or even a little update will cause a disaster.

1.Software setting

If you understand what’s the meaning of the instruction. You can do little modifications to it (like make -j15). Besides, it's suggested to follow this priority and build from the source.

1.1 UHD 4.0

git clone --branch UHD-4.0  https://github.com/ettusresearch/uhd.git uhd
mkdir uhd/host/build; cd uhd/host/build; cmake ..
make -j4
sudo make install

1.2 GNU Radio 3.8

git clone --branch maint-3.8 --recursive \ https://github.com/gnuradio/gnuradio.git 
mkdir gnuradio/build; cd gnuradio/build; cmake ..
make -j4
sudo make install

1.3 gr-ettus

git clone --branch maint-3.8-uhd4.0 
https://github.com/ettusresearch/gr-ettus.git gr-ettus
mkdir gr-ettus/build; cmake..
make -j4
sudo make install

1.4 Xilinx Vivado 2019.1

Get the web package from xilinx website.
Chmode +x the file
Excute it

After all, restart the computer and now we have the working environment.
We can do some tricks to verify them.

gnuradio-config-info

uhd_find_devices

If the result is wired, try this command to make sure usrp work correct.

uhd_usrp_probe

rfnocmodtool help

For uploading default image, please refer to the link below.
https://files.ettus.com/manual/page_usrp_x3x0.html

---

2.Create Custom FPGA Module with rfnocmodtool

I'm going to realize the "gain" module that example provided by UHD.
Let's start with creating the custom rfnoc block with rfnocmodtool.

rfnocmodtool newmod test1
cd rfnoc-test1
rfnocmodtool add gain
Enter name of block/code (without module name prefix): gain

Enter valid argument list, including default arguments: (leave blank)
Add Python QA Code? [y/N] N
Add C++ QA Code? [y/N] N
Block NoC ID (Hexadecimal):
Leaving blank results in random NoC ID
Skip Block Controllers Generation? [UHD block ctrl files] [y/N] N
Skip Block interface files Generation? [GRC block ctrl files] [y/N] N

In some situation you may able to skip the last two generation. Abstracted from "Getting Started with RFNoC Development"-AN-823 . It's worthy to note that though this file is for UHD3.0, there are some information that doesn't mention in "Getting_Started_with_RFNoC_in_UHD_4.0"-AN-400 .

• Block Controllers Generation:
  The block controllers are the C++ control that the user can apply to the UHD-part of the design. In these files, the user can add more control over this layer of the design. Depending on the complexity of the block it may be possible to add all necessary control using NoCScript (more details on NoCScript can be found in the section labeled UHD Integration). In this case the cpp/hpp block control files generation are not needed. Default is to generate as their existence will be ignored if not edited.

• Block Interface:
  Add more design specific functionality to the design at the GNU Radio interface by generating these block-interface files and adding necessary logic. Depending on the complexity of the block it may be possible to add all necessary control using NoC-Script. In this case the block-interface files are not needed. Default is to generate as their existence will be ignored if not edited.

Now we have the directory tree and we can divide it into three parts.

FPGA parts

• rfnoc/blocks
  • /blocks/
    • gain.yml – Block Description YAML
  • /fpga/rfnoc_block_gain/
    • rfnoc_block_gain.v – RFNoC Block HDL
    • rfnoc_block_gain_tb.sv – RFNoC Block Test Bench
    • noc_shell_gain.v – Custom NoC Shell
  • /icores/
    • gain_x310_rfnoc_image_core.yml – Image Core YAML, handling the whole RFNoC configurations.

---

Driver

• lib
  • gain_block_ctrl_impl.cpp – UHD Block Controller C++ code
  • gain_impl.cc – GNU Radio Block C++ code
• include/gain
  • gain_block_ctrl.hpp – UHD Block Controler C++ header
  • gain.h – GNU Radio Block C++ header

---

GnuRadio Application

• grc
  • test4gain_gain.block.yml - the block description in GunRadio
• examples
  • gain.grc – Example flowgraph of GunRadio using RFNoC Block
  • .py -GunRadio excute file

About this article that only talking about single I/O, we only need to program the FPGA part generally. The rest files are already done when the file structures are generated by rfnocmodtool.

3.Program custom FPGA module

3.1 block/gain.yml

For the project gain, it's not necessary to modify this file.
However, if the origin configuration can't satisfy you, like you want more ports. Editing the .yml file in /block folder as you wish. Then apply rfnoc_create_verilog.py to help you re-generate the corresponding .v file.

To have more details, our custom IP are wrapped by RFNoC and communcate to outside by noc_shell.v Thus modified I/O requires corresponding RFNoC file.

python3 ~/USRP_dep/uhd/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py -c ./adb.yml -d ~/USRP_dep/rfnoc-add1/rfnoc/fpga/rfnoc_block_adb

.v file

• rfnoc/fpga/rfnoc_block_gain
  • rfnoc_block_gain.v – RFNoC Block HDL
    Put your verilog code here.
  • noc_shell_gain
    If you re-configure the port, you should edit this depents on needs.
  • rfnoc_block_gain_tb.sv – RFNoC Block Test Bench
    Put your testbench here.

icore yml file

…

4.Cmake and test our IP.

Mkdir a build folder at <repo> and cmake inside. For me since the cmake required by Vivado is 3.3.2 rather than over 3.8 that UHD needed. We need to specify the uhd/fpga folder as well.

/usr/bin/cmake -DUHD_FPGA_DIR=~/USRP_dep/uhd/fpga ..

The result should be like this.

-- Checking for module SWIG
-- Found SWIG version 4.0.1.
-- Found SWIG: /usr/bin/swig4.0  
-- Registering RFNoC block: rfnoc_block_gain
-- Adding testbench target: rfnoc_block_gain_tb
-- Adding image core target: gain_x310_rfnoc_image_core
-- Configuring done
-- Generating done
-- Build files have been written to: /home/pieapple/USRP_dep/rfnoc-test4gain/build

Then we do the test bench by

make rfnoc_block_gain_tb    

It'll show the tb result.

========================================================
TESTBENCH STARTED: rfnoc_block_gain_tb
========================================================
[TEST CASE   1] (t =         0 ns) BEGIN: Flush block then reset it...
[TEST CASE   1] (t =      6450 ns) DONE... Passed
[TEST CASE   2] (t =      6450 ns) BEGIN: Verify Block Info...
[TEST CASE   2] (t =      6450 ns) DONE... Passed
[TEST CASE   3] (t =      6450 ns) BEGIN: Verify user register...
[TEST CASE   3] (t =      7850 ns) DONE... Passed
[TEST CASE   4] (t =      8425 ns) BEGIN: Test passing through samples...
[TEST CASE   4] (t =      9025 ns) DONE... Passed
========================================================
TESTBENCH FINISHED: rfnoc_block_gain_tb
 - Time elapsed:  9025 ns
 - Tests Run:     4
 - Tests Passed:  4
 - Tests Failed:  0
Result: PASSED      

Then we can build the image file.

make
sudo make install
make gain_x310_rfnoc_image_core  

or if you inster the debug probes, it'll be like:

rfnoc_image_builder -y ~/USRP_dep/rfnoc-add4/rfnoc/icores/add_x310_rfnoc_image_core.yml -t X310_1G -F ~/USRP_dep/uhd/fpga -l debug -I ~/USRP_dep/rfnoc-add4/rfnoc/blocks/add.yml

---

5.Programming bitstream and upload

After the image file building successfully, the .bin file will be in this directory.

<repo>/uhd/fpga/usrp3/top/x300/build/usrp_x310_fpga_HG.bit

Upload it.

uhd_image_loader --args "type=x300,addr=192.168.10.2" --fpga-path ./usrp_x310_fpga_1G.bin

An alternative method is viv_jtag_program or just using vivado. Generally, you only use this method when USRP bricks.

Re-power on the device and we can confirm the custom block by

uhd_usrp_probe

We can observe the Block#0 in FPGA right now.

|     _____________________________________________________
|    /
|   |       RFNoC blocks on this device:
|   |   
|   |   * 0/Block#0
|   |   * 0/DDC#0
|   |   * 0/DDC#1
|   |   * 0/DUC#0
|   |   * 0/DUC#1
|   |   * 0/Radio#0
|   |   * 0/Radio#1  

6.GRC yml

If your rfnoc port aren't 1 in out, which's the defalut setting and you're going to apply the rfnoc module with GnuRadio. Iti's necessary to modfiy the .grc yml to tell GnuRadio the correct port configure.

7.Result

Let's see the result by appling the RFNoC block in GnuRadio.

Reference

• RFNoC4 Workshop Part 2, Jonathon Pendlum – Ettus Research, Neel Pandeya – Ettus Research, GRCon 2020
• https://kb.ettus.com/Getting_Started_with_RFNoC_in_UHD_4.0
• https://kb.ettus.com/Getting_Started_with_RFNoC_Development
• https://wiki.gnuradio.org/index.php?title=Creating_Python_OOT_with_gr-modtool

–

tags: USRP, FPGA, Ettus Research, UHD, RFNoC, RFNoC搭建

[e-mail]
Department of Space Science & Engineering
Center for Astronautical Physics & Engineering
National Central University, Taiwan
PieappleJSun, Mar 27, 2022