# 資訊科技產業專案設計課程作業 3
## 工作機會
[Google Silicon Engineer](https://www.google.com/about/careers/applications/jobs/results/118043493233763014-silicon-engineer-university-graduate-2025?q=silicon&location=Taiwan&src=Online%2FHouse%20Ads%2FSKWS_LOC5&gad_source=1&gbraid=0AAAAA-TINRGm06unrdg7QDhZTgWPSy_VD&gclid=Cj0KCQiAi_G5BhDXARIsAN5SX7pzdILTb_oK9BwoQwCqlTZsU8PITfwDZzxGZ-Z4Zv9jHPUaSLoBrmgaAmNKEALw_wcB&target_level=EARLY&target_level=INTERN_AND_APPRENTICE)
<details>
<summary>詳細資訊</summary>

- Minimum qualifications:

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Academic coursework in computer architecture (e.g., core, cache, memory, etc.).
Experience with C/C++ or RTL.

- Preferred qualifications:

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
Experience designing/implementing or validating RTL design (e.g., core, cache, fabric, memory, codec, etc.).
Knowledge of OS, Firmware, or software stack.
Knowledge of performance or power architecture, power estimation, modeling, or optimization of processor or ASIC.
Excellent scripting language, C/C++ programming, and software design skills.

- About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

We welcome 2024 and 2025 graduates.

- Responsibilities

Perform performance validation and simulation using C/C++ and RTL-based models, and performance correlation.
Perform analysis results in both qualitative and quantitative fashion.
Create tools/scripts to automate test suites and models to improve functionality of simulators.
Participate in evaluation of future ASIC designs and general architecture.

</details>

[MTK Digital IC designer_Taipei (No Work Expe.)](https://careers.mediatek.com/eREC/JobSearch/JobDetail/MTK120191111002?returnUrl=%2FeREC%2FJobSearch%3FsortBy%3D%26order%3D%26page%3D1%26searchKey%3DRTL%26category%3D%26workExp%3D%26branch%3D%26program%3D)
<details>
<summary>詳細資訊</summary>

- Job Description

1. Digital design (RTL design, Synthesis, integration, verification)
2. SoC Chip design, integration
3. Familiar with VLSI design flow is a plus

- Requirement

1. Majored in electrical and electronics and Computer Science
2. Experience in VLSI courses is a plus
</details>

[【台北】AI加速器IC數位設計工程師(I6LD) ](https://www.104.com.tw/job/3nx06?jobsource=cs_2018indexpoc)

<details>
<summary>詳細資訊</summary>

- 【工作說明】

1. RISC-V coprocessor 架構設計
2. AI加速器架構設計
3. RTL實作

- 【必要條件】
1. 熟悉Computer Architecture like RISC-V, ARM, MIPS, etc.
2. 熟悉Verilog開發流程
- 【加分項目】
1. 熟悉IC設計後段流程，如synthesis/STA/LEC/DFT/…
2. 具有SIMD/DSP 開發經驗
3. 具有AI加速器實作經驗
</details>

## 職缺分析
- 基本上整個digital ic design flow都要碰過
- 要有實務經驗
- 像google要c + RTL co-design
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## 自我評估與分析
- 學歷：成大電機學+碩
- 課程：電機所VSD / AI on chip / systemc
- 經驗：RISC-V pipeline CPU, AXI, DRAM, CDC...
CNN based accelerator(simple version)
CNN & Transformer Unified accelerator(RTL & SystemC)
- 缺點
- 該碰的東西其實大部分都有碰過，但自覺不夠熟悉，無法清晰表達
- 無法講的professional

## 模擬面試
🧔：interviewer 👶：interviewee
### 基本問題
🧔：自我介紹
🧔：問履歷問題
問題著重於電機所的vlsi system design課程內容
有沒有碰過formal？
實驗室的加速器在做什麼？你負責哪部分，或是你做過什麼？
### 專業問題
🧔：因為我們是Edge TPU Team，所以問題著重於Low power與High performance的ai加速器
🧔：如何判斷加速器是否power efficiency？
舉例來說，現在有2個加速器
Ａ加速器2TOPs，Dynamic power是10W，Static power是5W
B加速器3TOPs，Dynamic power是12W，Static power是7W
哪一個比較power efficiency?
👶：A -> 2/(10+5) = 2/15
B -> 3/(12+7) = 3/19
所以是B比較power efficiency
🧔：matmul通常會卡在memory bound還是compute bound？
👶：如果是大矩陣，reuse rate高的話會是compute bound，反之則是memory bound

[resume](https://drive.google.com/file/d/1lWiaV7Blv8CBu_U0Dkeoz3uikdOnDz77/view?usp=sharing)