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數位電路設計––單智君
回目錄
第二章 Boolean Algebra and Logic Gates
n binary varibles -> 2^n distinct minterms -> 22n possible functions
Boolean expression (AND, OR, NOT)
Others type
ex.交換律、結合律…
Gate:
Extension to multiple inputs
AND, OR: commutative and associative
NAND, NOR: commutative but not associative
[(ABC)'*(DE)']' = ABC+DE ≠ (ABCDE)' = A'+B'+C'+D'+E'
XOR, Equivalence: commutative and associative
Positive Logic (H = 1) && Negative Logic (H = 0)
同一電路,正負邏輯會使邏輯閘代表意義互補(dual) eg.AND->OR
Integrated Circuits (ICs)
Levels (複雜度)
Families
important parameters (additional)
CAD tools -> Schematic capture tools -> Logic simulator -> Logic synthesizer
第三章 Gate-Level Minimization
F = AB+CD+CE -> 6 literals (stander form)
G = (A'+B)(B'+C)(C'+D)(D'+A) -> GIC = 12
- 2 var -> 2n = 4 minterms
- corresponding minterms have just one var different
F(A,B,C,D) = sigma m(0,1,2,5,7,8,9,10,14)
Verilog Model
synthesizable modules: describe hardware
testbench: check output result of module is correct
Sample of synthesizable modules:
ex:
module Name_Of_Module(inputA,inputB,inputC, outputD,outputE); // module name, parameters for all input and output
output outputD, outputE; // describe output
input inputA, inputB, inputC; // describe input
wire w1; // describe wire
/* GATE following, output is always be the first parameters /
and G1(w1,inputA,inputB); // this is an AND gate, G1 is gate name, w1 is output of gate, inputA and inputB is input
not G2(E,C); // NOT gate, E output, C input
or G3(D, w1, E); // OR gate
/ The order of above gate are NOT important */
endmodule
Sample of testbench:
ex:
module test_bench_name; // no input output
wire C, D; // output
reg A, B; // *input
Simulation waveforms (show the result)
`timescale 1ns/100ps
testbranch
boolean exprission
第四章 組合電路 Combinational Logic
gate設計流程:從問題轉成gate的方法:
binary 加法器:
半加器(half adder):把2個bit相加
加法器(full adder) :把3個bit相加(實踐起來會是兩個半加器)
設計方法:
加法器 Binary Ripple Carry Adder (n-bit Parallel Adder) (RCA)
使用Hierarchy & Iterative design,用n個full adder來湊
總共的Propagation-delay是2n+****1個gate-delay
但是速度太慢了,所以現實世界不會使用這種設計方法
加法器加速方法
[ ] Carry Lookahead Adder (CLA)
[ ] Gi = Ai Bi: 一定會有carry
[ ] Pi = Ai +Bi: 傳遞的carry跟傳入的carry相同
總共的Propagation-delay固定為6個gate-delay
binary 減法器:
A - B = A + (1's complement of B) + 1
用一個M來控制加法器的mode
M = 0 => A + B
M = 1 => A + B' + 1
處理overflow
十進位加法器:
binary 乘法器
比較器
編碼器 encoder
priority encoder:
優先順序可以任意自訂,這邊的設定為D3優先權最大
解碼器 decoder
Line Decoder
尾巴加個NOT就可以把minterm轉成maxterm
active HIGN: minterm
active LOW: maxterm
1-to-2-line decoder

2-to-4-line decoder

3-to-8-line decoder

enable input
Demultiplexer 解多工器(信號分離器)
任何有n個輸入和m個輸出的boolean function都可以用一個n-to-2^n-line decoder配上m個OR來實作
Multiplexer 多工器
three state gate (tri state gate?)
組合電路的HDL設計
設計規範:
三種設計模式:
兩種設計方法:
系統定義的12個gate:
4 value system:
output [0: 3] D:D是一個vector,有D[0], D[1], D[2], D[3]四個數,最高的bit(MSB)是D[0]
2005後的verilog可以將output, input的keyword直接寫在module的port list內
tri: 代表那條線路有多個driver(多輸出接在一起的,可能會出現z值)
**wire, wor, wand, tri, supply1, supply0,**多種線的定義
dataflow modeling
Behavioral modeling
數值表示:N'Bvalue
Test Branch
ch5 Synchronous Sequential Logic
同步電路:有管制改變時間(有閘門)、好設計
非同步電路:沒有管制、速度快、成本低
Latches:非同步,flip-flops的基本
SR Latch
S R Q+
0 0 Q
0 1 0
1 0 1
1 1 不應該發生
S'R' Latch
S R Q+
1 1 Q
1 0 0
0 1 1
0 0 不應該發生
with control
D Latch
moore model vs mealy model
HDL
新關鍵字:forever: 無限迴圈
always @(posedge wire1, negedge wire2)
<=: none blocking assignment, 所有 <= 會同時做
電路設計
狀態減少直接影響flip-flop數量
化簡方法:
小考