An unaligned memory access is a load/store that is trying to access an address location which is not aligned to the access size.
e.g: A load instruction trying to access 4 bytes from address 0x1 is an unaligned access. This typically gets split into two internal operations as shows in the following diagram and merges into one.
Note that in case of systems with caches, there can also be cases of addresses crossing a cache line boundary (a.k.a misaligned access) and some times accesses can also be crossing a page boundary.
Then you can also have other complexities like one half of the memory access is hit in cache while the other half is a miss in the cache. The load store execution unit along with cache controllers deals with these complexities but in summary it follows the same basic principle of merging two access
Some architectures (like Intel x86) also has alignment interrupts that help in detecting unaligned memory access.
考慮以下 unaligned_get32
函式的實作: (假設硬體架構為 32-bits)
「補完」對應的 unaligned_set8
函式:
參考資料: