# Dataflow Workshop
_Rennes, 12-14 December 2017_
<p align="center">
Created and Organized by: Karol Desnos & Jean-François Nezan
<table><tr><td><img src="https://www.insa-rennes.fr/typo3temp/_processed_/b/8/csm_logo_Insa_7154dd54b1.png" width=150px></td><td><img src="https://encrypted-tbn0.gstatic.com/images?q=tbn:ANd9GcRCc2xpqq2WBOUkbGnvr0eWkBDLrQtla7olSp9-p2UuUEYSMG_lIA" width=150px></td><td><img src="https://i.imgur.com/InFk7EQ.png" width=150px></td><td><img src="https://i.imgur.com/ncxKLT0.png" width=150px></td></td></tr></table>
</p>

## Logistic
### Location
The workshop will be hosted at INSA.
The exact address is:

   INSA Rennes
   20 Avenue des Buttes de Coësmes
   35708 Rennes, FRANCE

[\[==Google Maps==\]](https://www.google.com/maps?ll=48.120852,-1.635663&z=15&t=m&hl=fr&gl=GB&mapclient=embed&cid=7971114861046854862) [\[==Getting there by Car, Bus, Teleportation==\]](https://www.insa-rennes.fr/en/information/contact-location.html)

### Rooms
[\[==INSA Campus map==\]](https://www.insa-rennes.fr/fileadmin/ressources/Rubriques/PlanCampusINSA-Rennes_2017-2018.pdf)
The workshop will be held in the following rooms:
* *Amphitheatre GCU*:
* On Tuesday, the 12$^{th}$ and Wednesday the 13$^{th}$
* Located in Building 7. Entrance of the building is located on its North-East corner, facing Building 9.

* *Amphitheatre Bonnin*:
* On Thursday the 14$^{th}$
* Located in Building 5. Entrance of the building is located in the middle of its East face, facing Building 6.

### Hotels
We don't have any particular suggestions for hotels. The best option is to select a hotel near the city center, close to the "Republique" metro/bus station.
The bus system is very rapid in Rennes and can bring you to INSA in 15 minutes (Line C4 from [République](https://www.google.com/maps/place/R%C3%A9publique/@48.109684,-1.6814516,17z/data=!3m1!4b1!4m5!3m4!1s0x480ede349027416b:0x2171776be0777746!8m2!3d48.109684!4d-1.6792576?hl=fr)).
There are some hotel very close to INSA, but we don't think it's a very good option as they are a bit far away from all the restaurants and pubs from Rennes.

### Restaurants
Here is a list of "advised" restaurant in Rennes: [link](https://hackmd.io/MYdgzArARgplBmBaAnDAJmxAWEMKIEMAGYANkQEZ4YYsctoKsg==#)
_We have announced the restaurant for the Social Dinner below._

## Program Overview
_See [logistic](#rooms) section for the detailed room location_
_Last updated on 12.12.17 at 9:00_

## Social Dinner
The social dinner will take place in "Le Goût des Autres" Restaurant on Tuesday the 12th of December at 19:30.
[==\[Location\]==](https://www.google.fr/maps/place/Le+Gout+des+Autres/@48.1083882,-1.679421,17z/data=!3m1!4b1!4m5!3m4!1s0x480ede352823022d:0xca96c0c3b1e3406e!8m2!3d48.1083882!4d-1.6772323?dcr=0)

### Menu
**Registration closed**
The proposed 31€ menu will include:
* Aperitifs:
* Homemade Kir: Traditional french cocktail - [==\[Wikipedia\]==](https://en.wikipedia.org/wiki/Kir_(cocktail))
_Or_
* Non-alcoholic homemade cocktail
* Starters
* Fish Tartare in the Thaï Way,
_Or_
* Homemade semi-cooked foie gras and fig chutney.
* Main course
* Beef tenderloin, "grenaille" potatoes and chanterelles, gravy,
_Or_
* Noble fish, melted leeks and morels, creamy shellfish.
* Desserts
* Cheese from the master cheese ripener, jam & salad.
_Or_
* Lemon cream verrine and fontainebleau cream.

_Wine/Beer are not included in the menu but it'll be possible to order them separately._

## Detailed Program Description
Use the following Table of content to check the description of a presentation.

[toc]

## Tuesday 12th

### Shuvra - Prune
* 2017.12.12 | 10:10 - 10:40
* PRUNE: Dynamic and Decidable Dataflow for Signal Processing on Heterogeneous Platforms
* Shuvra Bhattacharryya (University of Maryland & Tampere University of Technology)
* Abstract:
The majority of contemporary mobile devices and personal computers are based on heterogeneous computing platforms that consist of a number of CPU cores and one or more Graphics Processing Units (GPUs). Despite the high volume of these devices, there are few existing programming frameworks that target full and simultaneous utilization of all CPU and GPU devices of the platform.

This talk presents a dataflow-flavored Model of Computation (MoC) that has been developed for deploying signal processing applications to heterogeneous platforms. The presented MoC is dynamic and allows describing applications with data dependent run-time behavior. On top of the MoC, formal design rules are presented that enable application descriptions to be simultaneously dynamic and decidable. Decidability guarantees compile-time application analyzability for deadlock freedom and bounded memory.

The presented MoC and the design rules are realized in a novel Open Source programming environment PRUNE and demonstrated with representative application examples from the domains of image processing, computer vision and wireless communications. Experimental results show that the proposed approach outperforms the state-of-the-art in analyzability, flexibility and performance.

This is joint work with Jani Boutellier (Tampere University of Technology), and Jiahao Wu (University of Maryland )

### Karol - Spider 4 MPPA
* 2017.12.12 | 10:40 - 11:05
* Porting the Spider Dataflow Runtime on the Kalray MPPA Manycore Architecture
* Karol Desnos (INSA/IETR)

### Carlo/Francesca - Exploiting
* 2017.12.12 | 11:20 - 11:50
* Exploiting Dataflows for Reconfigurable Hardware Accelerators
* Carlo Sau (UniCA), Francesca Palumbo (UniSS)
* Abstract:
The Multi-Dataflow Composer design suite for coarse-grained reconfigurable accelerators (baseline features and extensions: profiler, power manager, prototype) and use cases (similar applications involving common processing blocks, different working point for the same application, approximate computing).

### Hergys/Sébastien - Energy efficient
* 2017.12.12 | 11:50 - 12:20
* Energy efficient actor execution on heterogeneous architectures & Energy efficiency model generality in the context of embedded systems domain.
* Hergys Rexha & Sébastien Lafond (Abo Akademi)

### Johan - TBD
* 2017.12.12 | 14:00 - 14:30
* Title to be determined
* Johan Lilius (Abo Akademi)

### Kevin - Notifying
* 2017.12.12 | 14:30 - 14:55
* Notifying memories: a case-study on data-flow applications with NoC interfaces implementation
* Kevin Martin (Lab-Sticc)
* [DAC16 paper](https://dl.acm.org/citation.cfm?id=2898051)

### Srboljub - Quantifying
* 2017.12.12 | 15:10 - 15:30
* Quantifying the Interaction Between Structural Properties of Software and Hardware in the ARM big.LITTLE architecture
* Srboljub Stepanovic (Abo Akademi)
* Abstract
Heterogeneous architectures offer the opportunity to achieve high performance and energy efficiency by selecting appropriate cores for execution of ever changing software applications. Appropriate core selection depends on the interaction between the structural properties of the software and the hardware that influences performance of the software. We propose a model for efficient core selection when executing software on ARM’s big.LITTLE heterogeneous architecture. It features a metric based on the correlation between the performance and the number of last level data cache (LLC) misses on a big and a LITTLE core. Additionally our model defines a soft threshold in terms of the number of LLC misses that determines efficient core selection. We verify the model on both a stress benchmark (stress-ng) and a performance and energy demanding application (HEVC decoding) using XMEM and Linux perf dynamic tool.

### Hamza - Throughput
* 2017.12.12 | 15:30 - 15:55
* Throughput Evaluation of DSP Applications Based on Hierarchical Dataflow Models
* Hamza Deroui (INSA/IETR)

### Sudeep - Detecting
* 2017.12.12 | 16:10 - 16:40
* Detecting and scheduling SDFGs on CPU-GPU architectures
* Sudeep Kanur (Abo Akademi)
* [Technical Report](http://tucs.fi/publications/view/?pub_id=tKaLiEr17a)

### Mickaël - MultiRate
* 2017.12.12 | 16:40 - 17:05
* MultiRate Dataflow for FPGA programming. (work at National Instruments)
* Mickaël Dardaillon (INRIA, Ex-National Instruments)
## Wednesday 13th

### Alexandre - ADFG
* 2017.12.13 | 10:10 - 10:40
* ADFG: a scheduling synthesis tool for dataflow graphs in real-time systems
* Alexandre Honorat (INSA, ex-INRIA TEA)
* Abstract:
This talk introduces a synthesis tool of real-time system scheduling parameters: ADFG computes task periods and buffer sizes of systems as signal processing applications, resulting in a trade-off between throughput maximization and buffer size minimization. ADFG synthesizes systems modeled by ultimately cyclo-static dataflow (UCSDF) graphs, an extension of the standard CSDF model. One new synthesis algorithms for unconnected graphs is also introduced and evaluated.

### Wictor - Stream
* 2017.12.13 | 10:40 - 11:10
* Stream Scheduling on Platforms without Timing Guarantees
* Wictor Lund (Abo Akademi)
* Abstract:
The success of cloud computing is build on the fact that the computing platform is abstracted away and that the infrastructure can be shared. The abstraction of the computing platform requires that an a priori timing analysis of the application takes into account all possible microarchitectures, even future ones. The sharing of resources between different independent applications have the effect of making the availability of resources unpredictable. To schedule real-time streaming applications on cloud platforms, one need to know the how much capacity is available and how much resources the application needs at the moment.

I will present an an execution model for periodic tasks with soft real-time requirements on unpredictable platforms. The execution model provides a mechanism to measure how much load is on a system in presence of uncertain parameters such as the available capacity of the platform and the processing demand of a job.

### Ilkka - Dataflow
* 2017.12.13 | 11:25 - 11:45
* Dataflow framework for Transport Triggered Architectures
* Ilkka Hautala (University of Oulu)

### Julien - Preesm 4 MPPA
* 2017.12.13 | 11:45 - 12:10
* Hierarchical Dataflow Model for efficient programming of clustered manycore processors.
* Julien Hascoët (Kalray & INSA)
* [ASAP17 paper](https://hal.archives-ouvertes.fr/hal-01564019/file/ASAP-2017-Hierarchical-Dataflow-Model.pdf)

### Eduardo - Energy
* 2017.12.13 | 12:10 - 12:30
* Energy Consumption reduction and parallelism extraction on dataflow specifications for manycore platforms
* Eduardo Juarez (UPM)

### Jocelyn - CAPH
* 2017.12.13 | 14:00 - 14:30
* The CAPH HLS system. Current state and perspectives.
* Jocelyn Sérot (Institut Pascal)

### Maxime - Future
* 2017.12.13 | 14:30 - 14:50
* Future Directions on Models of Architecture
* Maxime Pelcat (INSA/Institut Pascal)

### Francesca/Carlo/Claudio - Future
* 2017.12.13 | 14:50 - 15:20
* The Future Directions of Dataflow-Based Reconfigurable Hardware Accelerators
* Francesca Palumbo (UniSS), Carlo Sau (UniCA), Claudio Rubattu (UniSS/INSA)
* Abstract:
The Multi-Dataflow Composer design suite extensions in term of High-Level Synthesis support (CAPH integration), run-time monitoring and reconfiguration triggering (MDC Papification), multi-grain possibilities (combination of fine- and coarse-grain reconfiguration), dataflow hardware-software partitioning (integration of MDC within PREESM), tagged dataflow exploration.

### Florian - Energy
* 2017.12.13 | 15:35 - 15:50
* Energy Consumption in Real-Time Reconfigurable Dataflow Applications
* Florian Arrestier (INSA/UPM)
* Abstract:
How can we reduce the overhead of realtime scheduling in dataflow applications ?
How optimize a scheduling energy wise instead of performance

### Ruben - From
* 2017.12.13 | 15:50 - 16:10
* From dataflow specifications to customised reconfigurable processors using HLS: the OpenCL case for SoC FPGAs
* Ruben Salvador (UPM)

### Alexandre - Extending
* 2017.12.13 | 16:10 - 16:25
* Extending dataflow models to improve multi-criteria static schedulability
* Alexandre Honorat (INSA)
* Abstract
Scheduling of simple dataflow models where only computation time and memory consumption are defined has already been widely studied. Power consumption is one of the new importnant metric to take into account in modern scheduling, as well as communications, preemptions, etc. The goal of this thesis is to extend the dataflow model with relevant metrics and to find associated multi-criteria scheduling heuristics.

### Hamza - Fully
* 2017.12.13 | 16:40 - 17:00
* Fully Modular Development of DSP Applications
* Hamza Deroui (INSA/Lip6)

### Nam - Contention
* 2017.12.13 | 17:00 - 17:20
* Contention-aware scheduling of synchronous data flow programs on a many-core architecture.
* Hai Nam - TRAN (INRIA)

## Thursday 14th

### Jeff - SKA
* 2017.12.14 | 10:10 - 10:30
* SKA (Square Kilometer Array): Need for Efficient Programming Tools
* Jean-François Nezan (INSA)

<div --% _Note that lunches on Tuesday, Wednesday and Thursday will be at INSA restaurant and will be paid by INSA, but the social dinner remains at your own expense._>

<div %closed

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