---
tags : 微算機與組合語言
---
###### 國立臺北大學資工系江宥旻
8088/8086 Microprocessors and Their Memory and Input/Output Interface
===
8088/8086 Microprocessors
---

Minimum-mode & Maximum-mode systems
---
:::success
**CPU去Memory抓Data和Instruction的簡略說明**
CPU$（CS\times16 + IP）$得到記憶體位址，CPU透過位址線$AD_0 \sim AD_{19}$送至ABL(DFF)，當ABL觸發時(ALE控制CLK)，把位址送去Memory，再利用Decoder解碼，讓記憶體知道資料是存在哪一塊，此時輸出會被Latch住，$AD_0 \sim AD_{19}$就可以當作資料線使用，取得資料或指令。
:::


四塊記憶體：$2^2$，用2個bit就可以區分資料在哪一塊
> 利用Decoder

:::info
$CS\times16+IP=46834H$
轉成二進制
$A_{19}A_{18}A_{17}A_{16}\cdot \cdot \cdot A_0$
$\quad0\quad1\quad0\quad0\cdot \cdot \cdot\quad0$
看$A_{19}$和$A_{18}$這兩個bit就好
$0K\sim255K:0000\cdot \cdot \cdot0\sim0011\cdot \cdot \cdot1$
$256K\sim511K:0100\cdot \cdot \cdot0\sim0111\cdot \cdot \cdot1$ ✌️
$512K\sim767K:1000\cdot \cdot \cdot1\sim1011\cdot \cdot \cdot1$
$768K\sim1023K:1100\cdot \cdot \cdot0\sim1111\cdot \cdot \cdot1$
:::

---

+ The meaning of pins
+ 3-state (三態閘)
1. High
2. Low
3. Floating 浮接：高阻抗(Z)

> 只要中斷，不管是NMI或INTR(NI)都會有對應的Interrupt Service Routine(ISR)，CPU就會去執行

 

+ $MI/\overline{MX}$
+ Minimum-mode (單核心)
+ Smaller and contain a single microprocessor
+ Maximum-mode (多核心)
+ Larger system and with multiprocessors

Minimum-mode interface signals
---

+ Staus signals
+ 
+ $S_5$：Internal Interrupt Enable Flag
+ $S_6$：Always 0
+ Control signals
+ IO/M(回顧Chapter1)、DT/R、SSO(Status output)、BHE(Bank High Enable)
+ RD、WR
+ DEN(Data Enable)：enables external devices to supply data to the microprocessor
+ READY：can be used to **insert wait states** into the bus cycle. It is ready to permit the data transfer to be completed
+ 若CPU的速度大於Memory的速度，則CPU就要等Memory，Memory的資料讀出來時就會發出READY訊號通知CPU
+ Interrupt signals
+ INTR、INTA
+ TEST：1 suspend operation and goes into what is known as the idle state, 0 execution resumes with next instruction in the program
+ NMI
+ RESET：is used to provide a hardware reset for the MPU, switching RESET to logic 0 initializes the internal register of the MPU and initiates a reset service routine
+ DMA interface signals
+ Direct Memory Access
+ IO acces policy (I/O和CPU的溝通，存取策略)
+ Polling 輪詢最慢(一個一個問)，但是最簡單，可是比較少人用(因為太慢了)
+ Interrupt 中斷(有問題的人直接舉手)
+ DMA 直接記憶體存取
+ HOLD、HLDA
+ $AD_0\sim AD_7$, $A_8\sim A_{15}$, $A_{16}\sim A_{19}$, SSO, IO/M, DT/R, RD, WR, DEN, INTR are all put into high-Z state

 

:::info
+ Polling I/O就是時不時過去看看水滾了沒。
+ Interrupted I/O就是水開了之後會發出高頻率的叫聲，像是以前的水壺會裝上一個通知水滾的尖嘴。
+ DMA I/O就是雇用了一個傭人幫忙煮開水，好了就拿過來主人的身邊。
:::

:::success
IN MOV太慢了，DMA直接記憶體存取$\Rightarrow$這樣就沒有CPU的局了
所以在DMA時，CPU不能動作(因為CPU、Memory和I/O是同個Bus，若CPU動作，則會影響存取的結果)，I/O會產生HOLD要求CPU不能動作，CPU同意會送出HLDA。
:::

Maximum-mode interface signals
---

**8288 Bus controller function block**

+ Meaning of $S_0\sim S_2$
+ 

System Clock
---
+ 8284 Clock Generator
+ Provide a system time base for synchronization of the internal and external operations of microprocessor
+ The value of CLK
+ **XTAL Divided by 3**
+ Block diagram of the 8284
+ 
+ CLK voltage and timing characteristics for a 5-MHZ processor 
+ Relationship between CLKand PCLK 

Bus cycle and time states
---
1. CPU執行指令所需要的週期：Instruction Cycle
2. CPU去Memory抓Data所需要的週期：Bus Cycle

> 一個Instruction Cycle可能有很多個Bus Cycle

+ Bus cycle
+ A cycle of microprocessor access external device
+ Memory or IO read/write
+ A **sequence of events** that start with an address being output on the system bus followed by a read or write data transfer
+ **Four time states** in 8088/8086 bus cycle
+ T1：put an address on the bus (送Address)
+ T2：put data on the data bus when write cycle or high-Z state when read cycle (送Data)
+ T3、T4：data available on data bus and get it into the MPU when read cycle or wait for peripheral get data completed (Data會在Data Bus，CPU再把資料讀進來)
+ Bus cycle during：125 x 4 = 500ns in an 8-MHz(CLK) 8088
+ $\frac{1}{freq}\times4$，乘4是因為$T_1\sim T_4$

+ Idle state (CPU沒有對Memory做存取的狀態)
+ No bus cycle required (Ex：Decoding)
+ On clock period long (一個CLK為一個單位)
+ Wait state
+ Response to a request by an event in external hardware instead of an internal event
+ $T_3\sim T_4$應該要把Data讀出來，若沒有$\Rightarrow T_3、T_4$就要有Wait state，等待Memory把Data送出來，CPU才不會取錯資料

> CPU越快$\Rightarrow$執行速度越快

:::success
**Example**
What is the during of the bus cycle in the 8088-based microprocessor if the clock is 8-MHz and two wait states are inserted？
**Solution**
$T_{cycle}=\frac{1}{freq}\times4+N\times\frac{1}{freq}=500ns+2\times125ns=750ns$
:::
> Memory若不夠大$\Rightarrow$有些Code就會放在硬碟，此時就需要Swapping的時間，所以Memory越大越好。

Hardware organization of the memory address space
---

**8088 and 8086 1MByte memory bank**
> 8088有8條資料線，8086有16條資料線(一次抓兩Byte的資料)

**8088 data transfer**
**8086 data transfer**
> $\overline{BHE}$ 決定讀取高位元組或低位元組

Memory Control Signals
---
**8088 minimum-mode memory control signals**
**Maximum mode memory control signals**

Read and write bus cycles
---
**8088 MN read bus cycle $\qquad\qquad\quad$ 8088 MN write bus cycle**
 

Memory interface CKT
---
**Address Bus Latches and Buffers**
**Bank write control logic**
**Bank read control logic**
> U$\Rightarrow$upper，L$\Rightarrow$lower

**Data bus transceivers**
 
> Buffer的用意是提高扇出數(高電流增益，推動後級元件)

**Address decoders**
TTL decoder
 

Programming Logic Arrays
---
+ Contains a general-purpose AND-OR-NOT array of logic gate circuits
+ Can be used to implement complex ckt instead of with separate logic gates
+ Logic gate can be programmable
+ EEPROM
+ PLD
+ Types of PLD devices
+ PLA
+ PAL
+ GAL
+ EPLD
+ CPLD
+ FPGA

**ROM**(Read Only Memory)
 

> ROM$\rightarrow$PROM(Programable)$\rightarrow$EPROM(Erasable)$\rightarrow$EEPROM(Electrical)


+ PLA (AND Array和OR Array都可燒)
+  
+ PAL (只有AND Array可燒)
+  

Types of Input/Output
---
**Types**
+ Isolated I/O
+ I/O devices are treated separate from memory
+ Isolate I/O address
+ I/O instruction
+ I/O control pin or bus
+ Memory-mapped I/O
+ Some of the memory address space is dedicated to I/O ports
:::spoiler
[Input/Outpot address space](https://hackmd.io/LaCSohjCTKSu2I3QOEH4fQ?view#InputOutpot-address-space)
:::

**Memory and I/O address space**
**Isolated I/O port**
+ Byte-wide & word-wide
+ page

> Port用來Data存取和控制

**Memory-mapped I/O ports**

Isolated Input/Output Interface
---
+ Types of I/O devices
+ Parallel port
+ 一次送8條或16條資料線(1Byte or 2Bytes)
+ serial port
+ 一次只送一條資料線(1bit)
+ Synchronous(同步)
+ Asynchronous(非同步)
+ I/O devices controller
+ Minimum-Mode Interface
+ Maximum-Mode Interface

參考資料
+ Barry B. Bery, “The Intel Microprocessors,” 8th Edition, 2009, Prentice Hall.
+ Walter A. Triebel, Avtar Singh, “The 8088 and 8086 Microprocessors – Programming, Interfacing, Software, Hardware, and Applications,” 4th Edition, 2003, Prentice Hall.
+ 國立臺北大學資工系張玉山教授ppt