# 2022 年「[資訊科技產業專案設計](https://hackmd.io/@sysprog/info2022)」作業 3
###### tags: `INFO2022`
## 職缺
### [MediaTek](https://careers.mediatek.com/eREC/): [智慧型手機 SoC 數位 IC 設計工程師](https://careers.mediatek.com/eREC/JobSearch/JobDetail/MTK120220316006?langKey=zh-TW)
- 職缺說明:
1. Architecture design and RTL implementation of Smartphone chipset
2. Smartphone SoC and mobile computing platform design
3. System bus and mobile peripheral design, integration, and modeling
4. SoC system performance analysis
5. SoC low power design, integration, and modeling
6. SoC adaptive voltage scaling development
- 職缺需求:
1. Familiar with digital IC design, DFT, and FPGA emulation flow
2. Experienced in SoC architecture, Embedded Processor(DSP/MCU), and bus (ARM bus) system architecture design is a plus
3. Experienced in chip integration is a plus
4. Experience with External Memory Interface design is a plus
5. Experience with system verification job is a plus
6. Experience with security hardware design is a plus
7. Experience with low power design is a plus
### [Realtek](https://www.realtek.com/zh-tw/): [CPU數位IC設計工程師](https://recruit.realtek.com/zh/index.php?option=com_content&view=article&id=10494)
- 工作項目
1. Knowledge of DSP, microprocessor and computer architecture fundamentals.
2. Experience in RTL design and ability to make trade-offs between power, performance and area appropriately.
3. Experience in the microprocessor design cycle: initial concept, micro-architecture, implementation, verification, documentation and support.
- 應徵條件：
1. 碩士以上; 電子、電機、資工、電信、電控、資科等相關科系畢業為主。
2. 具相關工作經驗者尤佳。
### [Google](https://tw.indeed.com/): [Silicon Engineer](https://careers.google.com/jobs/results/76766397218071238-silicon-engineer-university-graduate-2023/?src=Online%2FJob%20Board%2Findeed&utm_medium=job-posting&utm_source=indeed)
- Minimum qualifications:
1. Bachelor's degree in Engineering or equivalent practical experience.
2. Academic coursework in computer architecture (e.g., core, cache, memory, etc.).
3. Experience with C/C++ or RTL.
- Preferred qualifications:
1. Advanced degree in Computer Science, Electrical Engineering, or related field.
2. Experience designing/implementing or validating RTL design (e.g., core, cache, fabric, memory, codec, etc.).
3. Knowledge of OS, Firmware, or software stack.
4. Knowledge of performance or power architecture, power estimation, modeling, or optimization of processor or ASIC.
5. Excellent scripting language, C/C++ programming, and software design skills.
### [Amazon](https://www.amazon.jobs/en):[Software Engineer, Text-To-Speech (TTS)](https://www.amazon.jobs/en/jobs/2261340/software-engineer-text-to-speech-tts?fbclid=IwAR2upyboeXlMy12CxJZpJ9ZjWVvZjxfp7qegxDmu4VqxkKbiwVL4KwEYrbQ)
- Basic Qualifications
1. Experience contributing to the architecture and design (architecture, design patterns, reliability and scaling) of new and current systems
2. Non-internship professional software development experience
3. Programming experience with at least one modern language such as Java, C++, or C# including object-oriented design
4. 4+ years in a Software Engineer capacity.
- Preferred Qualifications
1. Strong software skills (including scripting languages).
2. Ability to communicate technical ideas with peers and non-technical peers;
3. Practical experience and knowledge of machine learning techniques and their application.
4. Experience in building Speech and/or NLP solutions;
5. Experience in developing and deploying machine learning techniques.
## 考古題
- [MediaTek](https://hackmd.io/tpspI4IYSROcE9ATbpH78g?both)
## 模擬面試
> 🧔：interviewer 👶：interviewee
### [Google](https://tw.indeed.com/): [Silicon Engineer](https://careers.google.com/jobs/results/76766397218071238-silicon-engineer-university-graduate-2023/?src=Online%2FJob%20Board%2Findeed&utm_medium=job-posting&utm_source=indeed)
🧔：Russell 你好，我是kevin，是今天這場面試的主持人，請你簡單自我介紹一下。
👶：Kevin你好，我來自台北，畢業於成功大學資訊工程研究所，研究所的主要研究領域是語音合成，成功開發的合成語言包含國語、台語、客語和印尼語。
🧔：請問你為什麼會想來面試這個職缺，是有相關的開發經驗嗎？
👶：在研究所有修過數位IC設計課程，對IC設計很有興趣和熱情，使用verilog實做過一些小型電路，例如:Pipeline CPU, LZ77 Encoder and Decoder, Edge-Based Line Average Interpolation 等......
🧔：好的，既然你有實作過 verilog 經驗的話，那麼請你幫我用C語言撰寫，在不使用division and mod情況下，判斷輸入一個非負整數是否為3的倍數，回傳Ture or False
👶：好的，在不使用division and mod情況下，我需要判斷一個非負整數是否可以被3整除
👶: 我會使用bitwise操作，
- 如果input=0 or 3，代表整除，return Ture
- 如果input<3，return False
- 如果input>3，則input必可以拆成 4a+b，且 a+b <=3
- Example:
- $4=4*1+0$ a=1, b=0
- $5=4*1+1$ a=1, b=1
- $9=4*2+1$ a=2, b=1
- 所以input>3時，$\frac{(4a+b)}{3} = a+\frac{(a+b)}{3}$
- $\frac{4}{3} = 1+\frac{1}{3}$
- $\frac{5}{3} = 1+\frac{2}{3}$
- $\frac{9}{3} = 2+\frac{(2+1)}{3}=3$

以下是我的操作步驟

// input n
// Step1: if n=0 or n=3, return Ture
// Stap2: if n<3, return False
// Step3: n>>2 + n&3
// step4: recursive
int isMult3(unsigned int n)
{
    if ( n == 0 || n == 3 )    
        return 1;
    if ( n < 3 ) 
        return 0;
    
    n = (n >> 2) + (n & 3);

    return(isMult3(n));
}

🧔: 那麼如果輸入可以為負整數的話，你該如何解決?
👶: 如果輸入可能為負的話，則在第一步先將負數轉成正數，因為只是判斷是否被3整除，所以正負號對結果沒有影響

// input n
// Step0: if n is negative, convert to positive
// Step1: if n=0 or n=3, return Ture
// Stap2: if n<3, return False
// Step3: n>>2 + n&3
// step4: recursive
int isMult3(int n)
{
    if (n>>31){
        n ^= -1;
        n += 1;
    }
    if ( n == 0 || n == 3 )    
        return 1;
    if ( n < 3 ) 
        return 0;
    
    n = (n >> 2) + (n & 3);

    return(isMult3(n));
}

🧔： 好的，那今天就先到這邊，謝謝你今天來參與我們的面試。
## 競爭能力
1. [Resume](https://drive.google.com/file/d/1AXEXkJD2eAwnF6cbrSePGC9XQ-cBc13l/view?usp=sharing)
2. C/C++、Verilog、python、flutter、MySQL、Web development
3. 使用 verilog 實作
- Pipeline CPU
- LZ77 Encoder and Decoder
- Edge-Based Line Average Interpolation
4. Text To Speech 的 Machine Learning 相關背景和實作經驗
- 使用 kaldi 和 HTS 開發國台語和客語的語音合成系統
- 在 GST-Tacotron1 基礎上，開發國台語情緒合成系統
- 在 Tacotron2 and WaveGlow 基礎上，開發國台語和印尼語合成系統
5. 使用 Flutter 框架開發
- 智能語音辨識KTV APP
- 語音助理APP(切喉者病患)
6. 使用 OpenCV 開發電腦視覺、影像處理
7. 研究所-智慧型醫學資訊系統實作教學助教
8. 計畫中使用 Linux 與C語言進行嵌入式系統開發
## 欠缺能力
- 英文口說能力須加強
- 對 Linux 開發不熟悉
- 欠缺實習或相關工作經驗
- 盲打的打字速度和正確性需要加強
- C/C++ 能力還需加強，例如:資料型態
- 有時不知道該如何將問題應用或舉例在實務上
- 對於一些基本的演算法不夠熟悉，例如:各種排序演算法
- 雖然有修過資工所數位IC設計課程，有Verilog實作經驗，但沒有持續開發Verilog