# Lab3: Reindeer - RISCV RV32I[M] Soft CPU

## Build Environment for RISC-V RV32I
It took me long time to figure out how to run program in Reindeer. In the begin, I try to use riscv-none-embed-gcc compile C code directly. But it seems use different start address with sumulation in Reindeer. Soft CPU can't access right instruction.

In Reindeer,we need to use RISC-V Compliance so that run simulation in Verilator. But the original Makefile which compile .S to .elf file isn't using [riscv-none-embed-] compiler. So we need to revise the Makefile in RISC-V Compliance.
Revise **Makefile** in the path`/home/joe/riscv-compliance/riscv-test-suite/rv32i`add line below.

TARGETDIR:=/home/joe/riscv-compliance/riscv-target
RISCV_TARGET:=riscvOVPsim
RISCV_DEVICE:=rv32i

Then add target filename into **Makefrag**

And **Makefile.include** in the path
`/home/joe/riscv-compliance/riscv-target/riscvOVPsim/device/rv32i`

ROOTDIR      ?= /home/joe/riscv-compliance

then change the target compiler

RISCV_PREFIX   ?= riscv-none-embed-

## Create the Assembly code file (.S)
Sum of N Natural Number, N=10

#include "compliance_test.h"
#include "compliance_io.h"
#include "test_macros.h"


RV_COMPLIANCE_RV32M


RV_COMPLIANCE_CODE_BEGIN

    RVTEST_IO_INIT

    RVTEST_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)

    RVTEST_IO_WRITE_STR(x31, "# Test Begin\n")

    # ---------------------------------------------------------------------------------------------

    RVTEST_IO_WRITE_STR(x31, "# Run Sum of first N number\n");

    	la      x1, N
	la      x2, test_res
	lw      x3, 0(x1)			#N
	main:                                   # @main
		
		li      x10, 0
		sw      x10, 0(x2)		#sum	
		li	x14, 0			#i
		j       Check
	Check:                                # =>This Inner Loop Header: Depth=1	
		blt     x3, x14, end		# if i<N	
		j       Loop
	Loop:                                #   in Loop: Header=BB0_1 Depth=1
		lw      x10, 0(x2)		
		add     x10, x10, x14		#sum = sum + i
		sw      x10, 0(x2)
		addi    x14, x14, 1		#i++		
		j       Check
	end:
		sw      x10, 0(x2)

    RVTEST_IO_CHECK()

    RVTEST_IO_ASSERT_GPR_EQ(x2, x10, 0x00000037)

    RVTEST_IO_WRITE_STR(x31, "# Test PASS!\n");

# ---------------------------------------------------------------------------------------------

RV_COMPLIANCE_HALT

RV_COMPLIANCE_CODE_END

    .data
	N:
	    .word 10


RV_COMPLIANCE_DATA_BEGIN

    .align 4

test_res:

    .fill 1, 4, -1

RV_COMPLIANCE_DATA_END

## Compile .S file
Put .S file in the path
`/home/joe/riscv-compliance/riscv-test-suite/rv32i/src`

Then, we can compile with **Makefile** revised earlier by use command below.

make SONN.elf


Elf and objdump fill will generate in
`/home/joe/riscv-compliance/work`

## Run simulation with Reindeer

Put elf file into `/home/joe/Reindeer/sim/compliance`
Go to the path`/home/joe/Reindeer/sim/verilator`use command

make test SONN

to run simulation and generate wavefrom file.


### Check wavefrom result
lw x3, 0(x1) -> x3 = **N** = 10

x10 -> **sum** = 1+2+3 =6
x14 -> **i** = 3

x10 -> **sum** = 55 (correct)
x14 -> **i**
**i** in 10 to 11, so get out of loop
brach is active

## How Reindeer works with Verilator


## Hold and Load