第六階段準備Litex 環境

# 第六階段準備Litex 環境 ## Install Litex ✅ https://github.com/enjoy-digital/litex/wiki/Installation ``` bash mkdir litex cd litex ``` ### UV https://docs.astral.sh/uv/getting-started/installation/ ```bash uv venv --seed source .venv/bin/activate ``` ### venv ```bash sudo apt install python3-venv python3 -m venv .litex . .litex/bin/activate ``` ```bash ./litex_setup.py --init --install git clone https://github.com/litex-hub/linux-on-litex-vexriscv.git ``` https://www.scala-sbt.org/1.x/docs/Installing-sbt-on-Linux.html#Installing+sbt+on+Linux ``` sudo apt install curl # Please Use These curl -s "https://get.sdkman.io" | bash sdk install java $(sdk list java | grep -o "\b8\.[0-9]*\.[0-9]*\-tem" | head -1) sdk install sbt ``` ## FPGA BitStream Build ✅ https://github.com/enjoy-digital/litex/wiki/Installation ``` ERROR: Could not detect Ninja v1.8.2 or newer ``` ``` pip3 install ninja ``` ## Simulation ✅ plase install Verilator on the git https://verilator.org/guide/latest/install.html ```bash= litex_sim --cpu-type=vexriscv litex_sim --cpu-type=vexriscv_smp ``` ### Linux Boot ✅ https://github.com/litex-hub/linux-on-litex-vexriscv/tree/master 1. Install the dtc tool ```bash= sudo apt-get install device-tree-compiler ``` 2. Create the dts & dtb file. (Use Sim.py) ``` cd litex git clone https://github.com/litex-hub/linux-on-litex-vexriscv.git cd linux-on-litex-vexriscv ./sim.py ``` 3. Generating the Linux binaries use the buildroot. ```bash cd litex git clone http://github.com/buildroot/buildroot cd buildroot make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_defconfig make ``` 4. Run the Sim.py Again. ``` cd litex cd linux-on-litex-vexriscv ./sim.py ``` 5. You just need wait an hour........ (took 1h 23m 54.1s on AMD RX7800X3D) ``` Warning: missing file ~/litex/linux-on-litex-vexriscv/buildroot/../images/rv32.dtb ``` 1. what is dtb https://breezetemple.github.io/2018/11/20/linux-dtb-and-boot/ https://stackoverflow.com/questions/21670967/how-to-compile-dts-linux-device-tree-source-files-to-dtb 2. Check the dts file ![image](https://hackmd.io/_uploads/BksefxKy1e.png) https://github.com/litex-hub/linux-on-litex-vexriscv/blob/69545456c5ccfbc88973107d64c1b7097c9f4c9b/sim.py#L137 ```bash= cd linux-on-litex-vexriscv/ ./sim.py ``` 4.AttributeError: 'str' object has no attribute 'removesuffix' ![image](https://hackmd.io/_uploads/B1izmeFyJg.png) ![image](https://hackmd.io/_uploads/rJEIQltk1g.png) upgrage the Ububtu to 22.04 , supported Python 3.9 6.Timescale missing on this module as other modules have it (IEEE 1800-2017 3.14.2.2) https://github.com/litex-hub/linux-on-litex-vexriscv/issues/314 https://verilator.org/guide/latest/install.html#git-install 7. Runing https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html https://verilator.org/guide/latest/simulating.html https://verilator.org/guide/latest/verilating.html ![image](https://hackmd.io/_uploads/rJnFsBa1ke.png) took 1h 23m 54.1s ## digilent_arty https://github.com/litex-hub/litex-boards https://www.controlpaths.com/2022/01/17/building-soc-litex/ #### arty a7 100t https://gist.github.com/ibndias/6f44d1d55251324f5b873436ad290ab3 #### arty a7 35t https://www.controlpaths.com/2022/03/28/running-linux-on-a-litex-soc/ https://jia.je/hardware/2023/04/19/litex-digilent-arty-a7/ https://www.taterli.com/9418 > It tooks (5m 37.5s) > ```bash= ./digilent_arty.py --build ``` ## OpenOCD Install ``` $ sudo apt install libtool automake pkg-config libusb-1.0-0-dev jimsh libjim-dev $ git clone https://github.com/ntfreak/openocd.git $ cd openocd $ ./bootstrap $ ./configure --enable-ftdi $ make $ sudo make install ``` ## digilent_arty Modify to Embedfire ✅ https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers/ ## Git Clone the litex-boards ✅ 1. Git Clone 2. litex_boars install ### Enviroments please use the ubuntu 22.04.5 https://ftp.ubuntu-tw.org/mirror/ubuntu-releases/22.04.5/ copy openocd/contrib/60-openocd.rules to /etc/udev/rules.d/ use `groups` check the user is in plugdev sudo udevadm control --reload-rules && sudo udevadm trigger add groups `sudo adduser $USER dialout` rename usb device https://www.rigacci.org/wiki/doku.php/doc/appunti/linux/sa/renaming_usb_devices `sudo nano /etc/udev/rules.d/10-local.rules` `ACTION=="add", ATTRS{idVendor}=="1a86", ATTRS{idProduct}=="7523", SYMLINK+="usbSerial"` `sudo udevadm control --reload-rules && sudo udevadm trigger` remove brltty (CH340 USBTTY) ```sudo apt purge brltty``` ### TODO (Wiil Add new Target to Here) ``` cd litex source .venv/bin/activate cd linux-on-litex-vexriscv ``` - [x] litex_boards - [x] platform - [x] boards - [x] Try Build : `python3 -m litex_boards.targets.embedfire_rise_pro --uart-baudrate=921600 --cpu-type=vexriscv_smp --cpu-variant=linux --build` - [x] Try Load : `python3 -m litex_boards.targets.embedfire_rise_pro --load` - [x] Try Flash: `python3 -m litex_boards.targets.embedfire_rise_pro --flash` - [x] litex_term - [x] ch340g : Use dmesg to check the is there any btltty ? - [x] ch340g : Use the latest Kernel form `sudo apt install linux-image-6.5.0-45-generic` - [x] LED Blink - [x] Build - [x] Load By OpenOCD - [x] Load By Vivado - [x] FPGA Example - [x] GPIO - [x] Buzzer (PWM) - [ ] EEPROM - [ ] Eth - [ ] HDMI Output - [ ] HDMI Input - [x] SD Card : `python3 -m litex_boards.targets.embedfire_rise_pro --uart-baudrate=921600 --cpu-type=vexriscv_smp --cpu-variant=linux --with-sdcard --build` - [ ] linux-on-litex-vexriscv - [x] Change the Dictionary : `cd linux-on-litex-vexriscv` - [x] Start the litex_term : `litex_term --speed=921600 --images=images/boot.json /dev/usbSerial` or `/dev/ttyUSB2` (You can use udev to rename the serial adpater) - [x] You must see the `litex>`, then key `serialboot` - [x] litex-bios - [x] LED Test - [x] SDRAM Test - [x] FPGA bit stream build (Linux) - [x] normal `./make.py --board embedfire_rise_pro --uart-baudrate 921600 --build` (need the dtb dts file) - [x] add jtagbone `./make.py --board embedfire_rise_pro --uart-baudrate 921600 --build` - [x] Image Build 1. `cd buildroocd t` 2. `make BR2_EXTERNAL=../linux-on-litex-vexriscv/buildroot/ litex_vexriscv_defconfig` 3. `make` - [x] OpenSBI - [x] [Host Bridge to control litex](/D1JJ8UEcSjyadWoKkrtQJw) - [x] uartbone - [x] `python3 -m litex_boards.targets.embedfire_rise_pro --uart-baudrate=921600 --uart-name=crossover --with-uartbone --cpu-type=vexriscv_smp --cpu-variant=linux --build --flash --load` - [x] `litex_server --uart --uart-port=/dev/usbSerial --uart-baudrate=921600` - [x] `litex_term crossover` - [x] jtagbone - [x] `python3 -m litex_boards.targets.embedfire_rise_pro --uart-baudrate=921600 --with-jtagbone --cpu-type=vexriscv_smp --cpu-variant=linux --build --load` - [x] `litex_server --jtag --jtag-config openocd_xc7_ft2232.cfg` - [x] `litex_cli --ident` - [x] [Use litexsope to debug soc](/MCYi6TdES6eTDcA36-TQZA) - [x] `litescope_cli -v main_leds 1` - [x] Learn https://github.com/enjoy-digital/litex/wiki/LiteX-for-Hardware-Engineers - [ ] [Use jtag to debug linux soc](/mpdEzmu6SiSPkY1yKgbweg) - [ ] Why libgpio set is not working ? - [x] Linux Boot - [x] litex_term - [x] SDCard - [ ] GPIO : [Use GPIO in Linux](/5p40uQkWQ6KPU-oRpCyppA) - [x] libgpio get - [ ] libgpio set - [ ] PWM : [Use PWM in Linux](/bYimwwfmSfmmfWddPb-bIw) ### Change to use PYZ update litex_boards ``` litex$ ./litex_setup.py --instal ``` build bitstream ``` python3 -m litex_boards.targets.tul_pynq_z2 --uart-baudrate=921600 --cpu-type=vexriscv_smp --cpu-variant=linux --build ``` load to fpga ``` python3 -m litex_boards.targets.tul_pynq_z2 --uart-baudrate=921600 --cpu-type=vexriscv_smp --cpu-variant=linux --load ```

Syntax	Example	Reference
# Header	Header	基本排版
- Unordered List	Unordered List
1. Ordered List	Ordered List
- [ ] Todo List	Todo List
> Blockquote	Blockquote
Bold font	Bold font
Italics font	Italics font
~~Strikethrough~~	~~Strikethrough~~
19^th^	19^th
H~2~O	H₂O
++Inserted text++	Inserted text
==Marked text==	Marked text
[link text](https:// "title")	Link
![image alt](https:// "title")	Image
`Code`	`Code`	在筆記中貼入程式碼
```javascript var i = 0; ```	`var i = 0;`
:smile:		Emoji list
{%youtube youtube_id %}	Externals
$L^aT_eX$	L^aT_eX
:::info This is a alert area. :::	This is a alert area.