This doc is just an attempt to get all our ducks in a row and put everything
together with sources. Everything with a ✅ should probably have a source.

Note that this doc isn't saying that we want to support everything with a checkmark,
this is just a place to collect what might be possible.

Platforms link: https://doc.rust-lang.org/nightly/rustc/platform-support.html

Table should cover all T1 & T2-hosttools targets. Compat:[1][2][3][4]

  • f128: C++ std::float128_t, C _Float128, LLVM fp128, GCC __float128
  • f16: C++ std::float16_t, C _Float16, LLVM half, GCC __fp16
  • f16b: C++ std::bfloat16_t, LLVM bfloat, GCC __bf16
  • f80: C/C++ long double[2:1], LLVM x86_fp80, GCC __float80
  • f64f64: C/C++ long double[2:2], LLVM ppc_fp128, GCC __ibm128, called double double
Platform f128 f16 f16b f80 f64f64 c_longdouble
arm-*-gnueabihf ❌ ⊛[5] 🪣[6] ❌ ❌ f64
armv7-*-gnueabihf ❌ ⊛[5:1] 🪣[6:1] ❌ ❌ f64
aarch64-*-!msvc ❌ ⊛[5:2] 🪣[6:2] ❌[7] ❌ f128
aarch64-*-msvc ❌ ⊛[5:3] 🪣[6:3] ❌[7:1] ❌ f64[8]
x86_32-*-!msvc 📃 ❌ ⊛[9] ❌,🪣⊛[10] ✅[2:3] ❌ f80[11]
x86_32-*-msvc ❌ ❌ ⊛[9:1] ❌ ❌[8:1] ❌ f64[8:2]
x86_64-*-!msvc 📃 ❌ ⊛[9:2] ❌,🪣⊛[10:1] ✅[2:4] ❌ f80[11:1]
x86_64-*-msvc ❌ ❌ ⊛[9:3] ❌ ❌[8:3] ❌ f64[8:4]
loongarch32 📗 ❌ f128
loongarch64-*-gnu 📗[12] ❌[12:1]⊛[9:4] ❌[12:2] ❌[12:3] ❌[12:4] f128
loongarch64-*-softfl 📗[12:5] ❌[12:6]⊛[9:5] ❌[12:7] ❌[12:8] ❌[12:9] f128
mips-*-gnu 📗 ❌[13] 🪣⊛[14] ❌[13:1] ❌[13:2] ❌[13:3] f64[15]
mipsel-*-gnu 📗 ❌[13:4] 🪣⊛[14:1] ❌[13:5] ❌[13:6] ❌[13:7] f64[15:1]
mips64-*-gnuabi64 📗 ❌[13:8] 🪣⊛[14:2] ❌[13:9] ❌[13:10] ❌[13:11] f128
mips64el-*-gnuabi64 📗 ❌[13:12] 🪣⊛[14:3] ❌[13:13] ❌[13:14] ❌[13:15] f128
powerpc-*-gnu ⊛[16] ⊛[17] ⊛[17:1] ⊛[18] 📗[19] f64f64/f128[20]
powerpc64-*-gnu ⊛[16:1] ⊛[17:2] ⊛[17:3] ⊛[18:1] 📗[19:1] f64f64/f128[20:1]
riscv64gc-*-gnu ⊛[21] ⊛[22] ❌ ❌ ❌ f128
s390x-*-gnu ✅[23] ❌[23:1]⊛[9:6] ❌[23:2] ❌[23:3] ❌[23:4] f128
  • ✅: supported with hardware acceleration
  • 📗: supported with soft float, ABI defines type / operations for that type
  • 🪣: supported only as a storage format (f16b is a truncated f32), or some instruction support but no to-size FPU
  • 📃: Glibc 2.26+ provides a soft float implementation[24]
  • 📒: Other soft float implementation used by GCC/LLVM (not glibc)
  • ⊛: sometimes supported or with features, see note
  • ❌: Not supported, type will not exist
  • ?: this needs double checking

  1. https://llvm.org/docs/LangRef.html#floating-point-types ↩︎ ↩︎

  2. https://gcc.gnu.org/onlinedocs/gcc-13.1.0/gcc/Floating-Types.html ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  3. https://gcc.gnu.org/onlinedocs/gcc/Half-Precision.html ↩︎

  4. https://en.cppreference.com/w/cpp/types/floating-point ↩︎

  5. BFP16 support introduced in ARMv8.2 for both 32-bit and 64-bit ARM[29] ↩︎ ↩︎ ↩︎ ↩︎

  6. https://releases.llvm.org/16.0.0/tools/clang/docs/LanguageExtensions.html#half-precision-floating-point ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  7. https://developer.apple.com/documentation/swift/float80 ↩︎ ↩︎

  8. https://learn.microsoft.com/en-us/cpp/cpp/fundamental-types-cpp?view=msvc-170#floating-point-types ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  9. LLVM does support 16-bit floats on all targets as a storage only format[6:5] ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  10. BFP is supported as a storage format on x86 if SSE2 is available[1:1] ↩︎ ↩︎

  11. Default to f80.
    The size of f80 is 12 on x86_32.
    The size of f80 is 16 on x86_64.
    Can be switched to one of f128/f64/f80 depends on compilers option according to [19:3]. ↩︎ ↩︎

  12. https://github.com/loongson/la-abi-specs/blob/release/lapcs.adoc ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  13. https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00083-2B-MIPS64INT-AFP-06.01.pdf ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  14. Only supported with MSA[31] extension, introduced with MIPS R5. ↩︎ ↩︎ ↩︎ ↩︎

  15. O32 ABI has f64 as longdouble ↩︎ ↩︎

  16. Only supported with BFP128 feature, introduced with PowerISA v3.0[25] ↩︎ ↩︎

  17. Only supported with VSX on PowerISA v3.1+ (conversions only)[25:1] or with SVP64 (full HW support)[26] ↩︎ ↩︎ ↩︎ ↩︎

  18. Some HW support with BFP128 feature – supports emulating f80 by using f128 hardware in round-to-odd mode with xsrqpxp instruction that rounds to f80 ↩︎ ↩︎

  19. https://gcc.gnu.org/wiki/Ieee128PowerPC ↩︎ ↩︎ ↩︎ ↩︎

  20. Default to f64f64 currently.
    The default will be f128 once the transition finished according to [2:5] and [30].
    Can be switched to one of f128/f64/f64f64 depends on compilers option according to [19:2] ↩︎ ↩︎

  21. Only supported with Q extension[27] ↩︎

  22. Only supported with Zfh or Zfhmin extensions for RISC-V according to [28].
    For ARM the supproted arch are according to [6:4] ↩︎

  23. https://linux.mainframe.blog/zarchitecture-principles-of-operation/ SA22-7832-13 ↩︎ ↩︎ ↩︎ ↩︎ ↩︎ ↩︎

  24. https://sourceware.org/git/?p=glibc.git;a=blob;f=NEWS;hb=81325b12b14c44887f1633a2c180a413afc2b504#l143 ↩︎

  25. https://files.openpower.foundation/s/dAYSdGzTfW4j2r2 ↩︎ ↩︎

  26. https://git.libre-soc.org/?p=libreriscv.git;a=blob;f=openpower/sv/rfc/ls005.xlen.mdwn;hb=5e573680771f7a041d93d394003d6f9f08177a98#l131 ↩︎

  27. https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2023-05-23/src/q-st-ext.adoc ↩︎

  28. https://github.com/riscv/riscv-isa-manual/blob/riscv-isa-release-2023-05-23/src/zfh.adoc ↩︎

  29. https://developer.arm.com/documentation/den0024/a/Porting-to-A64/Data-types ↩︎

  30. https://fedoraproject.org/wiki/Changes/PPC64LE_Float128_Transition ↩︎

  31. https://s3-eu-west-1.amazonaws.com/downloads-mips/documents/MD00868-1D-MSA64-AFP-01.12.pdf ↩︎

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