# Assignment:RISC-V Assembly and Instruction Pipeline
## Problem description
Given an array nums with n objects colored red, white, or blue, sort them in-place so that objects of the same color are adjacent, with the colors in the order red, white, and blue.

We will use the integers 0, 1, and 2 to represent the color red, white, and blue, respectively.

Example 1:

Input: nums = [2,0,2,1,1,0]
Output: [0,0,1,1,2,2]
Example 2:

Input: nums = [2,0,1]
Output: [0,1,2]
Example 3:

Input: nums = [0]
Output: [0]
Example 4:

Input: nums = [1]
Output: [1]
...

#### c code

#include<stdio.h>
int main(){
  int i, j, temp;
  int nums[9]={0,1,1,1,2,2,2,0,1,0};
  int numsSize=9;
	for (i = numsSize-1; i >=0; --i){     
        for (j = 0; j < i ; ++j){  
			if (nums[j] > nums[j + 1])       {
				temp = nums[j];
				nums[j] = nums[j + 1];
				nums[j + 1] = temp;
			}
 		}
	}
}

#### assembly code

.data
list:  .word 0,2,7,4,5,6,3,8,1
len:   .word 9
cma:   .string ","
ent:   .string "\n"
.text


main:
    la    s1, list
    lw    s2, len
    addi  s9, s2, -1
    add   s3, zero, zero   # i = 0 (s3)
    add   s4, s1, zero     # t1 = list[i]  address (s4)
loop1:
    addi  s5, s3, 0        # j = i+1 (s5)
    add   s6, s4, zero     # t2 = list[j]  address (s6)
loop2:
    addi  s5, s5, 1
    addi  s6, s6, 4        # j = j+1
    lw    t1, 0(s4)        # value of list[i]
    lw    t2, 0(s6)        # value of list[j]
    blt   t1, t2, loop2_
    sw    t2, 0(s4)
    sw    t1, 0(s6)
loop2_:
    blt   s5, s9, loop2
    addi  s3, s3, 1
    addi  s4, s4, 4        # i = i+1
    blt   s3, s9, loop1

    la    a0, ent          # new line
    li    a7, 4            # print
    ecall
showList:
    lw    t1, 0(s1)
    add   a0, t1, zero     # load  integer
    li    a7, 1            # print result
    ecall
    la    a0, cma          # speration
    li    a7, 4            # print
    ecall
    addi  s1, s1, 4
    addi  s2, s2, -1
    bgtz  s2, showList

    li   a7, 10           #end program
    ecall

#### Five-stage pipeline in RISC-V: IF-ID-EX-MEM-WB
Here are multiple processer models which can be selected in Ripes, the following image shows RISC-V 5-Stage Processor model.

The “5-stage” means this processor using five-stage pipeline to parallelize instructions. The stages are:

1.Instruction fetch (IF)
2.Instruction decode and register fetch (ID)
3.Execute (EX)
4.Memory access (MEM)
5.Register write back (WB)

#### IF:
In this stage,it will fetch instruction and decide the next Program Counter.

Before the previos step, PC get the instruction address 0x00000038, so now output PC is 0x00000038

Since there is no “Jump” or “Branch” instruction before, PC will increase 4 then get the next address 0x0000003c
Finally, all of the data (include PC and instruction address) will enter NEXT pipeline register


#### ID:
This stage,it will decode the instruction and read the register content action.


#### EX:

Because of previos instruction, it occurs data hazard ,so it needs to stall and clear all data in EXE stage.

#### MEM:
Pass the value 0x10000020 to MEM/WB.
Because this instruction doesn’t need to do anything about data access, memory write light is 0 and show red
Finally, all of data (PC and result) will enter MEM/WB pipeline register.

#### WB:
This stage,it will write back the result(from ALU calculation and data memory) into Register.
The value 0x00000002 will be passed to register.