# Lab2: RISC-V RV32I[MA] emulator with ELF support for 9*9t able
###### tags: `Computer Architecture`
## 9*9 multiplication table
### problems encountered
when I tried to write a C program on this emulator,I found some problems.
* #### Problem1 : It can't be compiled.
>Once there is an instruction about load/store $sp in My assembly code. My program becomes uncompiled immediately. Because the $sp is initial located at 0x0000000. At this moment, the program will be wrong at this instruction addi sp,sp,-464 , the position will be negative and the program will be uncompiled.
* #### solution
>It is because the RISCV emulator doesn't have an OS on it. When we executing our program. The stack point($sp) is set in the wrong position. Hence, we have to write a Bootloader to tell Compiler which position should be started. In the below, the code means initial out register. And load the start point into $sp.
The code below is my setup.s. We have to write this to load $sp correctly
```=
#Define constants
.section .text
.align 4
.global _start
_start:
li x1, 0
li x2, 0
li x3, 0
li x4, 0
li x5, 0
li x6, 0
li x7, 0
li x8, 0
li x9, 0
li x10, 0
li x11, 0
li x12, 0
li x13, 0
li x14, 0
li x15, 0
li x16, 0
li x17, 0
li x18, 0
li x19, 0
li x20, 0
li x21, 0
li x22, 0
li x23, 0
li x24, 0
li x25, 0
li x26, 0
li x27, 0
li x28, 0
li x29, 0
li x30, 0
li x31, 0
init_stack:
la sp, _stack
Init:
jal __start
j Exit
Exit:
ecall
ret
```
The code below is the Linker file. We must have a link file to tell Compiler how I place the section. And the most important is that we must put our setup file in front of the TEXT section. Otherwise, the program will still access the wrong position.
```=
_STACK_SIZE = DEFINED (_STACK_SIZE) ? _STACK_SIZE : 0x1000;
MEMORY{
mem : ORIGIN = 0x00000000, LENGTH = 0x0000100
mem2 : ORIGIN = 0x00000100, LENGTH = 0x0010000
}
ENTRY(_start)
SECTIONS{
/*setup.o(.text) should put in front of the *(.text), because setup.o is initiall file.We should initial first*/
.text : {
setup.o(.text);
*(.text);
*(.text.*);
} > mem2
.data : {
. = ALIGN(4) ;
__data_paddr_start = LOADADDR(.data);
__data_start = .;
*(.data);
*(.data.*);
*(.gnu.linkonce.d.*)
__data_end = .;
} > mem2
.stack : {
. = ALIGN(4);
_stack_end = .;
. += _STACK_SIZE;
_stack = .;
} > mem2
}
```
#### Problem2 : Can't use mul instruction
After I accomplished the linker script and setup.s, It didn’t run correctly. On the other hand, it can be compiled, but it stopped at the position where I use mul instruction.
#### Solution :
After a long time discussion with my friend, we found that this emulator doesn't allow the user to use mul instruction. Below is a part C code of the riscv emulator. Which indicate the reason for my problem.
```
1379 case 0x33: /* OP */
1380
1381 imm = insn >> 25;
1382 val = reg[rs1];
1383 val2 = reg[rs2];
1384 #ifndef STRICT_RV32I
1385 if (imm == 1) {
1386 funct3 = (insn >> 12) & 7;
1387 switch(funct3) {
1388 case 0: /* mul */
1389 #ifdef DEBUG_EXTRA
1390 dprintf(">>> MUL\n");
```
The problem is at line 1384 #ifndef STRICT_RV32I. I'm sure that the variable imm is equal to 1. But I can not enter the if block. That is the problem is. Hence, I check line 1384. If I want to use mul instruction. STRICT_RV32I should not be defined. But line 98 indicates that STRICT_RV32I is defined. It makes the program not to enter line 1384. However, we slash this line and the program is solved.
```
97 /* added by Shaos: */
98 //#define STRICT_RV32I
99 #define FALSE (0)
100 #define TRUE (-1)
```
the assebly code with compiler optimization
```=
.file "test1.c"
.option nopic
.text
.section .rodata
.align 2
.LC0:
.string "Hello RISC-V!\n"
.align 2
.LC1:
.string "*"
.align 2
.LC2:
.string "="
.align 2
.LC3:
.string "\n"
.text
.align 2
.globl __start
.type __start, @function
__start:
addi sp,sp,-464
sw s0,460(sp)
addi s0,sp,464
li a5,1073750016
sw a5,-20(s0)
lui a5,%hi(.LC0)
addi a5,a5,%lo(.LC0)
sw a5,-24(s0)
lui a5,%hi(.LC1)
addi a5,a5,%lo(.LC1)
sw a5,-28(s0)
lui a5,%hi(.LC2)
addi a5,a5,%lo(.LC2)
sw a5,-32(s0)
lui a5,%hi(.LC3)
addi a5,a5,%lo(.LC3)
sw a5,-36(s0)
sw zero,-40(s0)
sw zero,-44(s0)
li a5,5
sw a5,-40(s0)
li a5,3
sw a5,-44(s0)
lw a5,-28(s0)
lbu a4,0(a5)
lw a5,-20(s0)
sb a4,0(a5)
lw a4,-40(s0)
lw a5,-44(s0)
mul a6,a4,a5
sw a5,-452(s0)
lw a5,-32(s0)
lbu a4,0(a5)
lw a5,-20(s0)
sb a4,0(a5)
nop
lw s0,460(sp)
addi sp,sp,464
jr ra
.size __start, .-__start
.ident "GCC: (xPack GNU RISC-V Embedded GCC, 64-bit) 8.2.0"
```
Assembly Code without O3 optimization
```=
.file "test1.c"
.option nopic
.text
.section .rodata
.align 2
.LC0:
.string "Hello RISC-V!\n"
.align 2
.LC1:
.string "*"
.align 2
.LC2:
.string "="
.align 2
.LC3:
.string "\n"
.text
.align 2
.globl __start
.type __start, @function
__start:
addi sp,sp,-464
sw s0,460(sp)
addi s0,sp,464
li a5,1073750016
sw a5,-32(s0)
lui a5,%hi(.LC0)
addi a5,a5,%lo(.LC0)
sw a5,-36(s0)
lui a5,%hi(.LC1)
addi a5,a5,%lo(.LC1)
sw a5,-40(s0)
lui a5,%hi(.LC2)
addi a5,a5,%lo(.LC2)
sw a5,-44(s0)
lui a5,%hi(.LC3)
addi a5,a5,%lo(.LC3)
sw a5,-48(s0)
sw zero,-20(s0)
sw zero,-24(s0)
li a5,1
sw a5,-20(s0)
j .L2
.L5:
li a5,1
sw a5,-24(s0)
j .L3
.L4:
lw a4,-20(s0)
lw a5,-24(s0)
mul a3,a4,a5
lw a4,-20(s0)
mv a5,a4
slli a5,a5,2
add a5,a5,a4
slli a5,a5,1
lw a4,-24(s0)
add a5,a5,a4
slli a5,a5,1
lw a4,-24(s0)
add a5,a5,a4
slli a5,a5,2
addi a4,s0,-16
add a5,a4,a5
sw a3,-436(a5)
lw a5,-24(s0)
addi a5,a5,1
sw a5,-24(s0)
.L3:
lw a4,-24(s0)
li a5,9
ble a4,a5,.L4
lw a5,-20(s0)
addi a5,a5,1
sw a5,-20(s0)
.L2:
lw a4,-20(s0)
li a5,9
ble a4,a5,.L5
li a5,1
sw a5,-20(s0)
j .L6
.L12:
li a5,1
sw a5,-24(s0)
j .L7
.L11:
sw zero,-464(s0)
sw zero,-460(s0)
lw a4,-20(s0)
mv a5,a4
slli a5,a5,2
add a5,a5,a4
slli a5,a5,1
lw a4,-24(s0)
add a5,a5,a4
slli a5,a5,2
addi a4,s0,-16
add a5,a4,a5
lw a5,-436(a5)
sw a5,-28(s0)
j .L8
.L10:
lw a4,-28(s0)
li a5,10
rem a5,a4,a5
sw a5,-460(s0)
lw a4,-28(s0)
li a5,9
ble a4,a5,.L9
lw a4,-28(s0)
li a5,10
rem a5,a4,a5
sw a5,-464(s0)
.L9:
lw a4,-28(s0)
li a5,10
div a5,a4,a5
sw a5,-28(s0)
.L8:
lw a5,-28(s0)
bgtz a5,.L10
lw a5,-20(s0)
andi a5,a5,0xff
addi a5,a5,48
andi a5,a5,0xff
sb a5,-455(s0)
lw a5,-24(s0)
andi a5,a5,0xff
addi a5,a5,48
andi a5,a5,0xff
sb a5,-456(s0)
addi a5,s0,-455
sw a5,-52(s0)
lw a5,-52(s0)
lbu a4,0(a5)
lw a5,-32(s0)
sb a4,0(a5)
lw a5,-40(s0)
lbu a4,0(a5)
lw a5,-32(s0)
sb a4,0(a5)
addi a5,s0,-456
sw a5,-52(s0)
lw a5,-52(s0)
lbu a4,0(a5)
lw a5,-32(s0)
sb a4,0(a5)
lw a5,-44(s0)
lbu a4,0(a5)
lw a5,-32(s0)
sb a4,0(a5)
lw a5,-464(s0)
andi a5,a5,0xff
addi a5,a5,48
andi a5,a5,0xff
sb a5,-453(s0)
lw a5,-460(s0)
andi a5,a5,0xff
addi a5,a5,48
andi a5,a5,0xff
sb a5,-454(s0)
addi a5,s0,-453
sw a5,-52(s0)
lw a5,-52(s0)
lbu a4,0(a5)
lw a5,-32(s0)
sb a4,0(a5)
addi a5,s0,-454
sw a5,-52(s0)
lw a5,-52(s0)
lbu a4,0(a5)
lw a5,-32(s0)
sb a4,0(a5)
lw a5,-48(s0)
lbu a4,0(a5)
lw a5,-32(s0)
sb a4,0(a5)
lw a5,-24(s0)
addi a5,a5,1
sw a5,-24(s0)
.L7:
lw a4,-24(s0)
li a5,9
ble a4,a5,.L11
lw a5,-20(s0)
addi a5,a5,1
sw a5,-20(s0)
.L6:
lw a4,-20(s0)
li a5,9
ble a4,a5,.L12
nop
lw s0,460(sp)
addi sp,sp,464
jr ra
.size __start, .-__start
.ident "GCC: (xPack GNU RISC-V Embedded GCC, 64-bit) 8.2.0"
```
Below is compile with -O3 optimization and result
```
riscv-none-embed-gcc -march=rv32im -mabi=ilp32 -O3 -nostdlib -c setup.s
riscv-none-embed-gcc test1.c setup.o -march=rv32im -mabi=ilp32 -O3 -nostdlib -T link.ld -o test1
./emu-rv32i test1
1*1=01
1*2=02
1*3=03
1*4=04
1*5=05
1*6=06
1*7=07
1*8=08
1*9=09
2*1=02
2*2=04
2*3=06
2*4=08
2*5=10
2*6=12
2*7=14
2*8=16
2*9=18
3*1=03
3*2=06
3*3=09
3*4=12
3*5=15
3*6=18
3*7=21
3*8=24
3*9=27
4*1=04
4*2=08
4*3=12
4*4=16
4*5=20
4*6=24
4*7=28
4*8=32
4*9=36
5*1=05
5*2=10
5*3=15
5*4=20
5*5=25
5*6=30
5*7=35
5*8=40
5*9=45
6*1=06
6*2=12
6*3=18
6*4=24
6*5=30
6*6=36
6*7=42
6*8=48
6*9=54
7*1=07
7*2=14
7*3=21
7*4=28
7*5=35
7*6=42
7*7=49
7*8=56
7*9=63
8*1=08
8*2=16
8*3=24
8*4=32
8*5=40
8*6=48
8*7=56
8*8=64
8*9=72
9*1=09
9*2=18
9*3=27
9*4=36
9*5=45
9*6=54
9*7=63
9*8=72
9*9=81
>>> Execution time: 962384 ns
>>> Instruction count: 2130 (IPS=2213253)
>>> Jumps: 110 (5.16%) - 20 forwards, 90 backwards
>>> Branching T=98 (31.61%) F=212 (68.39%)
```
Below is the result with compiler optimization
```
riscv-none-embed-gcc -march=rv32im -mabi=ilp32 -nostdlib -c setup.s
riscv-none-embed-gcc test1.c setup.o -march=rv32im -mabi=ilp32 -nostdlib -T link.ld -o test1
./emu-rv32i test1
1*1=01
1*2=02
1*3=03
1*4=04
1*5=05
1*6=06
1*7=07
1*8=08
1*9=09
2*1=02
2*2=04
2*3=06
2*4=08
2*5=10
2*6=12
2*7=14
2*8=16
2*9=18
3*1=03
3*2=06
3*3=09
3*4=12
3*5=15
3*6=18
3*7=21
3*8=24
3*9=27
4*1=04
4*2=08
4*3=12
4*4=16
4*5=20
4*6=24
4*7=28
4*8=32
4*9=36
5*1=05
5*2=10
5*3=15
5*4=20
5*5=25
5*6=30
5*7=35
5*8=40
5*9=45
6*1=06
6*2=12
6*3=18
6*4=24
6*5=30
6*6=36
6*7=42
6*8=48
6*9=54
7*1=07
7*2=14
7*3=21
7*4=28
7*5=35
7*6=42
7*7=49
7*8=56
7*9=63
8*1=08
8*2=16
8*3=24
8*4=32
8*5=40
8*6=48
8*7=56
8*8=64
8*9=72
9*1=09
9*2=18
9*3=27
9*4=36
9*5=45
9*6=54
9*7=63
9*8=72
9*9=81
>>> Execution time: 934900 ns
>>> Instruction count: 9820 (IPS=10503797)
>>> Jumps: 388 (3.95%) - 126 forwards, 262 backwards
>>> Branching T=284 (64.11%) F=159 (35.89%)
```
### C code
```=
void __start()
{
volatile char* tx = (volatile char*) 0x40002000;
const char* show1 = "*";
const char* show2 = "=";
const char* show3 = "\n";
int ans[10][10];
int i=0,j=0;
char k,k1;
char s,s1;
char *d;
int x[2];
int temp;
for(i=1;i<10;i++){
for(j=1;j<10;j++){
ans[i][j] = i * j;
}
}
for(i=1;i<10;i++){
for(j=1;j<10;j++){
x[0]=0;
x[1]=0;
temp = ans[i][j];
while(temp>0){
x[1]=temp%10;
if((temp/10)>0){
temp = temp/10;
x[0]=temp%10;
}
temp = temp/10;
}
s = (int) (i+48);
s1= (int) (j+48);
d = &s;
*tx = *d;
*tx = *show1;
d = &s1;
*tx = *d;
*tx = *show2;
k = (int) (x[0]+48);
k1= (int) (x[1]+48);
d = &k;
*tx = *d;
d = &k1;
*tx = *d;
*tx = *show3;
}
}
}
```
### objdump
>use riscv-none-embed-objdump -d test1 to see how the text section allocated. It is important that setup file(_start) is in front of the my C program.
>
```=
test1: file format elf32-littleriscv
Disassembly of section .text:
00000100 <_start>:
100: 00000093 li ra,0
104: 00000113 li sp,0
108: 00000193 li gp,0
10c: 00000213 li tp,0
110: 00000293 li t0,0
114: 00000313 li t1,0
118: 00000393 li t2,0
11c: 00000413 li s0,0
120: 00000493 li s1,0
124: 00000513 li a0,0
128: 00000593 li a1,0
12c: 00000613 li a2,0
130: 00000693 li a3,0
134: 00000713 li a4,0
138: 00000793 li a5,0
13c: 00000813 li a6,0
140: 00000893 li a7,0
144: 00000913 li s2,0
148: 00000993 li s3,0
14c: 00000a13 li s4,0
150: 00000a93 li s5,0
154: 00000b13 li s6,0
158: 00000b93 li s7,0
15c: 00000c13 li s8,0
160: 00000c93 li s9,0
164: 00000d13 li s10,0
168: 00000d93 li s11,0
16c: 00000e13 li t3,0
170: 00000e93 li t4,0
174: 00000f13 li t5,0
178: 00000f93 li t6,0
0000017c <init_stack>:
17c: 00001117 auipc sp,0x1
180: 31410113 addi sp,sp,788 # 1490 <_stack>
00000184 <Init>:
184: 010000ef jal ra,194 <__start>
188: 0040006f j 18c <Exit>
0000018c <Exit>:
18c: 00000073 ecall
190: 00008067 ret
00000194 <__start>:
194: e4010113 addi sp,sp,-448
198: 00600593 li a1,6
19c: 00c00613 li a2,12
1a0: 01200793 li a5,18
1a4: 00800693 li a3,8
1a8: 00400313 li t1,4
1ac: 00900813 li a6,9
1b0: 01000893 li a7,16
1b4: 1b212a23 sw s2,436(sp)
1b8: 1b312823 sw s3,432(sp)
1bc: 1b712023 sw s7,416(sp)
1c0: 19812e23 sw s8,412(sp)
1c4: 19912c23 sw s9,408(sp)
1c8: 19a12a23 sw s10,404(sp)
1cc: 00300c93 li s9,3
1d0: 00200d13 li s10,2
1d4: 00500c13 li s8,5
1d8: 00700993 li s3,7
1dc: 00a00b93 li s7,10
1e0: 00e00913 li s2,14
1e4: 00100e13 li t3,1
1e8: 1a812e23 sw s0,444(sp)
1ec: 1a912c23 sw s1,440(sp)
1f0: 1b412623 sw s4,428(sp)
1f4: 1b512423 sw s5,424(sp)
1f8: 1b612223 sw s6,420(sp)
1fc: 01400a93 li s5,20
200: 19b12823 sw s11,400(sp)
204: 03c12623 sw t3,44(sp)
208: 03912a23 sw s9,52(sp)
20c: 02612c23 sw t1,56(sp)
210: 04b12023 sw a1,64(sp)
214: 05012623 sw a6,76(sp)
218: 04612c23 sw t1,88(sp)
21c: 04b12e23 sw a1,92(sp)
220: 06c12423 sw a2,104(sp)
224: 06f12a23 sw a5,116(sp)
228: 07912e23 sw s9,124(sp)
22c: 08b12023 sw a1,128(sp)
230: 03a12823 sw s10,48(sp)
234: 03812e23 sw s8,60(sp)
238: 05312223 sw s3,68(sp)
23c: 04d12423 sw a3,72(sp)
240: 05a12a23 sw s10,84(sp)
244: 06d12023 sw a3,96(sp)
248: 07712223 sw s7,100(sp)
24c: 07212623 sw s2,108(sp)
250: 07112823 sw a7,112(sp)
254: 09012223 sw a6,132(sp)
258: 0b512a23 sw s5,180(sp)
25c: 0d512c23 sw s5,216(sp)
260: 01900a93 li s5,25
264: 01800713 li a4,24
268: 01500493 li s1,21
26c: 02400513 li a0,36
270: 01c00413 li s0,28
274: 02000f93 li t6,32
278: 02300393 li t2,35
27c: 02800f13 li t5,40
280: 02a00293 li t0,42
284: 00f00b13 li s6,15
288: 01e00a13 li s4,30
28c: 03000e93 li t4,48
290: 01b00c93 li s9,27
294: 0d512e23 sw s5,220(sp)
298: 02d00a93 li s5,45
29c: 08c12423 sw a2,136(sp)
2a0: 08f12823 sw a5,144(sp)
2a4: 08912a23 sw s1,148(sp)
2a8: 08e12c23 sw a4,152(sp)
2ac: 0a612223 sw t1,164(sp)
2b0: 0ac12623 sw a2,172(sp)
2b4: 0ae12c23 sw a4,184(sp)
2b8: 0a812e23 sw s0,188(sp)
2bc: 0df12023 sw t6,192(sp)
2c0: 0e712223 sw t2,228(sp)
2c4: 0fe12423 sw t5,232(sp)
2c8: 0eb12a23 sw a1,244(sp)
2cc: 0ec12c23 sw a2,248(sp)
2d0: 03600593 li a1,54
2d4: 0ef12e23 sw a5,252(sp)
2d8: 10e12023 sw a4,256(sp)
2dc: 10512623 sw t0,268(sp)
2e0: 03100613 li a2,49
2e4: 09612623 sw s6,140(sp)
2e8: 09912e23 sw s9,156(sp)
2ec: 0ad12423 sw a3,168(sp)
2f0: 0b112823 sw a7,176(sp)
2f4: 0ca12223 sw a0,196(sp)
2f8: 0d812623 sw s8,204(sp)
2fc: 0d712823 sw s7,208(sp)
300: 0d612a23 sw s6,212(sp)
304: 0f412023 sw s4,224(sp)
308: 0f512623 sw s5,236(sp)
30c: 11412223 sw s4,260(sp)
310: 10a12423 sw a0,264(sp)
314: 11d12823 sw t4,272(sp)
318: 10b12a23 sw a1,276(sp)
31c: 04800313 li t1,72
320: 03f00d93 li s11,63
324: 12c12a23 sw a2,308(sp)
328: 14e12623 sw a4,332(sp)
32c: 03800613 li a2,56
330: 04000713 li a4,64
334: 16f12823 sw a5,368(sp)
338: 05100793 li a5,81
33c: 12912223 sw s1,292(sp)
340: 12812423 sw s0,296(sp)
344: 12712623 sw t2,300(sp)
348: 12512823 sw t0,304(sp)
34c: 15f12823 sw t6,336(sp)
350: 15e12a23 sw t5,340(sp)
354: 16e12023 sw a4,352(sp)
358: 16612223 sw t1,356(sp)
35c: 17012623 sw a6,364(sp)
360: 18b12023 sw a1,384(sp)
364: 18612423 sw t1,392(sp)
368: 11312e23 sw s3,284(sp)
36c: 13212023 sw s2,288(sp)
370: 12c12c23 sw a2,312(sp)
374: 13b12e23 sw s11,316(sp)
378: 14d12223 sw a3,324(sp)
37c: 15112423 sw a7,328(sp)
380: 02c10293 addi t0,sp,44
384: 15d12c23 sw t4,344(sp)
388: 14c12e23 sw a2,348(sp)
38c: 17912a23 sw s9,372(sp)
390: 16a12c23 sw a0,376(sp)
394: 17512e23 sw s5,380(sp)
398: 19b12223 sw s11,388(sp)
39c: 18f12623 sw a5,396(sp)
3a0: 03100f13 li t5,49
3a4: 00a00713 li a4,10
3a8: 00900593 li a1,9
3ac: 06400e13 li t3,100
3b0: 06300313 li t1,99
3b4: 40002837 lui a6,0x40002
3b8: 02a00493 li s1,42
3bc: 03d00413 li s0,61
3c0: 00a00393 li t2,10
3c4: 03a00f93 li t6,58
3c8: 00028e93 mv t4,t0
3cc: 03100893 li a7,49
3d0: 0440006f j 414 <__start+0x280>
3d4: 02e7e7b3 rem a5,a5,a4
3d8: 03060613 addi a2,a2,48
3dc: 0ff67613 andi a2,a2,255
3e0: 03078793 addi a5,a5,48
3e4: 0ff7f793 andi a5,a5,255
3e8: 01e80023 sb t5,0(a6) # 40002000 <_stack+0x40000b70>
3ec: 00980023 sb s1,0(a6)
3f0: 01180023 sb a7,0(a6)
3f4: 00880023 sb s0,0(a6)
3f8: 00c80023 sb a2,0(a6)
3fc: 00f80023 sb a5,0(a6)
400: 00188893 addi a7,a7,1
404: 00780023 sb t2,0(a6)
408: 0ff8f893 andi a7,a7,255
40c: 004e8e93 addi t4,t4,4
410: 03f88663 beq a7,t6,43c <__start+0x2a8>
414: 000ea783 lw a5,0(t4)
418: 06f05663 blez a5,484 <__start+0x2f0>
41c: 00000613 li a2,0
420: 02e7c6b3 div a3,a5,a4
424: faf5d8e3 bge a1,a5,3d4 <__start+0x240>
428: 03c7c533 div a0,a5,t3
42c: 02e6e633 rem a2,a3,a4
430: faf352e3 bge t1,a5,3d4 <__start+0x240>
434: 00050793 mv a5,a0
438: fe9ff06f j 420 <__start+0x28c>
43c: 001f0f13 addi t5,t5,1
440: 0fff7f13 andi t5,t5,255
444: 02828293 addi t0,t0,40
448: f91f10e3 bne t5,a7,3c8 <__start+0x234>
44c: 1bc12403 lw s0,444(sp)
450: 1b812483 lw s1,440(sp)
454: 1b412903 lw s2,436(sp)
458: 1b012983 lw s3,432(sp)
45c: 1ac12a03 lw s4,428(sp)
460: 1a812a83 lw s5,424(sp)
464: 1a412b03 lw s6,420(sp)
468: 1a012b83 lw s7,416(sp)
46c: 19c12c03 lw s8,412(sp)
470: 19812c83 lw s9,408(sp)
474: 19412d03 lw s10,404(sp)
478: 19012d83 lw s11,400(sp)
47c: 1c010113 addi sp,sp,448
480: 00008067 ret
484: 03000793 li a5,48
488: 03000613 li a2,48
48c: f5dff06f j 3e8 <__start+0x254>
```
#### readelf
```
$ riscv-none-embed-readelf -h test1
```
result
```
ELF Header:
Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, little endian
Version: 1 (current)
OS/ABI: UNIX - System V
ABI Version: 0
Type: EXEC (Executable file)
Machine: RISC-V
Version: 0x1
Entry point address: 0x100
Start of program headers: 52 (bytes into file)
Start of section headers: 1676 (bytes into file)
Flags: 0x0
Size of this header: 52 (bytes)
Size of program headers: 32 (bytes)
Number of program headers: 1
Size of section headers: 40 (bytes)
Number of section headers: 8
Section header string table index: 7
```
#### size
```
$ riscv-none-embed-size test1
```
```
text data bss dec hex filename
912 0 4096 5008 1390 test1
```
#### instruction state
with optimization
```
Instructions Stat:
LUI = 1
AUIPC = 1
JAL = 11
JALR = 1
BEQ = 81
BNE = 9
BGE = 220
LW = 93
SB = 567
SW = 93
ADDI = 521
ANDI = 252
ECALL = 1
LI* = 166
DIV = 139
REM = 139
Five Most Frequent:
) SB = 567 (26.62%)
2) ADDI = 521 (24.46%)
3) ANDI = 252 (11.83%)
4) BGE = 220 (10.33%)
5) LI* = 166 (7.79%)
```
### instruction state without optimization
```
Instructions Stat:
LUI = 1
AUIPC = 1
JAL = 103
JALR = 1
BLT = 162
BGE = 281
LW = 2927
LBU = 567
SB = 891
SW = 1133
ADDI = 1770
ANDI = 648
SLLI = 486
ADD = 486
ECALL = 1
LI* = 614
MUL = 81
DIV = 139
REM = 139
Five Most Frequent:
1) LW = 2927 (29.81%)
2) ADDI = 1770 (18.03%)
3) SW = 1133 (11.54%)
4) SB = 891 (9.08%)
5) ANDI = 648 (6.60%)
```
| | Compile with -O3| Compile without optimization |
| -------- | -------- | -------- |
| total instruction | 2130 | 9818 |
|Jump |110|388|
|Jump forwards|20|126|
|Jump backwards|90|262|
|Branch True|98|284|
|Branch False|212|159|
As you can see, after optimization we reduce a lot of total instruction, jump, and branch. But Branch false is increased after optimization.
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