# BL630 Software-based self testing Paper Sharing

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- 本網頁蒐集、整理**黃俊郎 教授**實驗室(BL630)的研究生們報告、討論或發表之論文。
- 本網頁將相關論文分為以下兩個領域:
- Software-based self-test (SBST)
- Automatic test pattern generation (ATPG)
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## SBST Related Papers

| Name | Year of Publication | Citations | Published in | Slide |
|:-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------:|:-------------------:|:---------:|:---------------------------------------------------------------------------------------------------------:| ----------------------------------------------------------------------------------------------------------------------------------------------- |
|[Automatic Test Program Generation for Transition Delay Faults in Pipelined Processors](https://ieeexplore.ieee.org/document/9808811)| 2021 | - | IEEE International Test Conference in Asia (ITC-Asia) | -|
| [Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors](https://ieeexplore.ieee.org/document/4212148) | 2007 | 19 | IEEE Transactions on VLSI Systems | [link](https://docs.google.com/presentation/d/1NnEl-nLmK9eClqmVPqFH-OC721oHyINU/edit?usp=sharing&ouid=111324361008229366232&rtpof=true&sd=true) |
| [A Flexible Framework for the Automatic Generation of SBST Programs](https://ieeexplore.ieee.org/document/7440859) | 2016 | 30 | IEEE Transactions on VLSI Systems | [link](https://docs.google.com/presentation/d/1RvXqjFRRoT_Ql0rQy2LlD8fPJs-6S__C/edit?usp=sharing&ouid=111324361008229366232&rtpof=true&sd=true) |
| [Fault-Independent Test-Generation for Software-Based Self-Testing](https://ieeexplore.ieee.org/document/8474081) | 2018 | 2 | IEEE International Symposium on On-Line Testing And Robust System Design (IOLTS) | [link](https://docs.google.com/presentation/d/1UcyIgKE8xA38qFnXXtpfAG72AfxrV37N/edit?usp=sharing&ouid=111324361008229366232&rtpof=true&sd=true) |
| [Systematic software-based self-test for pipelined processors](https://ieeexplore.ieee.org/document/1688828) | 2006 | 22 | ACM/IEEE Design Automation Conference | [link](https://drive.google.com/file/d/1gIirah8yIA6F2LYaqwM98O1Qoc7QCgkf/view?usp=sharing) |
| [Automated mapping of pre-computed module-level test sequences to processor instructions](https://ieeexplore.ieee.org/document/1583987) | 2005 | 25 | IEEE International Conference on Test | [link](https://drive.google.com/file/d/1Kk5fD0NmTLa-2m7qfNIaREavdG2mBzFD/view?usp=sharing) |
| [Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product](https://ieeexplore.ieee.org/document/9138983) | 2020 | 2 | 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) | [link](https://drive.google.com/file/d/1geaoqmlbTDIVIi4yMxrmQwUJpKWqNkZZ/view?usp=sharing) |
| [An effective approach for functional test programs compaction](https://ieeexplore.ieee.org/document/7482466) | 2016 | 4 | 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) | [link](https://drive.google.com/file/d/1OJigv7BIDFysV4ekKwLojiGweBw6GVb-/view?usp=sharing) |
| [Implementation-Independent Functional Test Generation for RISC Microprocessors](https://ieeexplore.ieee.org/abstract/document/8920323) | 2019 | 2 | 2019 IFIP/IEEE 27th International Conference on VLSI-SoC | [link](https://drive.google.com/file/d/1w3G2-B1Oc_3lwSlTPMdkkgw3j4dc7qC1/view?usp=sharing) |
| [Automatic Test Program Generation Using Executing-Trace-Based Constraint Extraction for Embedded Processors](https://ieeexplore.ieee.org/abstract/document/6265421) | 2013 | 30 | IEEE Transactions on VLSI Systems | [link](https://drive.google.com/file/d/18ZD8lwZi77QI5kP490th7HEVIfw7u1JL/view?usp=sharing) |
| [Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors](https://ieeexplore.ieee.org/document/8599062) | 2020 | 1 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | [link](https://drive.google.com/file/d/1vt89awyCqpyrlCayKa9QzaYnjEJny8FN/view) |
| [Automatic Pattern-to-Program Conversion Methodology for Software-Based Self-Test](https://drive.google.com/file/d/19DLw3yebKTDt2nBFwBLPSZND__r2IBJv/view) | 2020 | - | Bo-Yi Yang's work | - |
| [Microprocessor Software-Based Self-Testing](https://ieeexplore.ieee.org/document/5396292) | 2010 | 174 | IEEE Design & Test of Computers | [link](https://docs.google.com/presentation/d/1YQnwYMxAenzo9iSHe45Pw-962vHehF4x/edit?usp=sharing&ouid=111324361008229366232&rtpof=true&sd=true) |

## ATPG Related Papers

| Name | Year of Publication| Citations | Published in | Slide |
|:------------------------------------------------------------------------------------------:|:--------------:|:---------:|:-------------------------------:| ----------------------------------------------------------------------------------------------------------------------------------------------- |
| [HOPE: an efficient parallel fault simulator for synchronous sequential circuits](https://ieeexplore.ieee.org/document/536711) | 1996 | 121 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems| [link](https://drive.google.com/file/d/1fAZ8yklFaDJrs8DxYATHurLI5K9kGrf8/view?usp=sharing) |
| [A Test Pattern Generation methodology for low power consumption](https://ieeexplore.ieee.org/document/670912) | 1998 | 54 | 16th IEEE VLSI Test Symposium | [link](https://drive.google.com/file/d/1_Wb-VwOO4v91yhUsozBl5W3Q9moKKrHA/view?usp=sharing) |
| [Diagnostic test generation for small delay defect diagnosis](https://ieeexplore.ieee.org/document/5496730) | 2010 | 2 | Proceedings of 2010 International Symposium on VLSI Design, Automation and Test | [link](https://docs.google.com/presentation/d/1TKoiIhzrbQmkJxxOPOvrGTI8evrupw8H/edit?usp=sharing&ouid=111324361008229366232&rtpof=true&sd=true) |
| [An efficient fault simulation technique for transition faults in non-scan sequential circuits](https://ieeexplore.ieee.org/document/5012098) | 2009 | 4 | 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems | [link](https://drive.google.com/file/d/1yr1N6pVLiqbh09ZiPrcPJu1lSX2b0B71/view?usp=sharing) |
| [Sequential Test Generation Based on Preferred Primary Input Cubes](https://ieeexplore.ieee.org/document/7469862) | 2016 | 7 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems | [link](https://drive.google.com/file/d/1BF0naUtD6zj4IyFq5ifRdO5XbNc4pv4A/view?usp=sharing) |
| [SAT-ATPG using preferences for improved detection of complex defect mechanisms](https://ieeexplore.ieee.org/document/6231098) | 2012 | 11 | 2012 IEEE 30th VLSI Test Symposium | [link](https://drive.google.com/file/d/1hsHYD9S6tEfC8IE8Qd1_jo9wp4lAP9pP/view?usp=sharing) |
| [Effective and Efficient Test Pattern Generation for Small Delay Defect](https://ieeexplore.ieee.org/document/5116618) | 2009 | 39 | 2009 27th IEEE VLSI Test Symposium | [link](https://drive.google.com/file/d/1pllT6oz6PxCwJwMhJ1Y6IMMJcARytitT/view?usp=sharing) |
| [PROOFS: a fast, memory efficient sequential circuit fault simulator](https://ieeexplore.ieee.org/document/114913) | 1990 | 61 | 27th ACM/IEEE Design Automation Conference | [link](https://drive.google.com/file/d/1kqInY4F5AMM0-1DY0LMtlRQ4gDTqGqbx/view?usp=sharing) |