# 積體電路設計實驗 Lab01

code on EDA Playground

module CC(
  in_n0,
  in_n1,
  in_n2,
  in_n3,
  in_n4,
  in_n5,
  opt,
  equ,
  out_n
);


input [3:0] in_n0, in_n1, in_n2, in_n3, in_n4, in_n5;
input [2:0] opt;
input equ;
output [3:0] out_n;

wire [3:0] out0, out1, out2, out3, out4, out5;

OPT opt1(.in_n0(in_n0), .in_n1(in_n1), .in_n2(in_n2), .in_n3(in_n3), .in_n4(in_n4), .in_n5(in_n5), .opt(opt), .out_n0(out0), .out_n1(out1), .out_n2(out2), .out_n3(out3), .out_n4(out4), .out_n5(out5));

wire [3:0] final_out;

EQU equ1(.in_n0(out0), .in_n1(out1), .in_n2(out2), .in_n3(out3), .in_n4(out4), .in_n5(out5), .equ(equ), .out_n(final_out));

endmodule



//--------------------------------------------------------------
//Module OPT & EQU
//--------------------------------------------------------------
module OPT(
  in_n0,
  in_n1,
  in_n2,
  in_n3,
  in_n4,
  in_n5,
  opt,
  out_n0,
  out_n1,
  out_n2,
  out_n3,
  out_n4,
  out_n5
);

input [3:0] in_n0, in_n1, in_n2, in_n3, in_n4, in_n5;
input [2:0] opt;
output wire [3:0] out_n0, out_n1, out_n2, out_n3, out_n4, out_n5;


assign out_n0 = in_n0;
assign out_n1 = in_n1;
assign out_n2 = in_n2;
assign out_n3 = in_n3;
assign out_n4 = in_n4;
assign out_n5 = in_n5;


endmodule

module EQU(
  in_n0,
  in_n1,
  in_n2,
  in_n3,
  in_n4,
  in_n5,
  equ,
  out_n
);

input[3:0] in_n0, in_n1, in_n2, in_n3, in_n4, in_n5;
input equ;
output[3:0] out_n;

assign out_n = in_n0;

endmodule


//Ｑ：為什麼有些可以用assign，有些不行？？

code for testbench

module test;
  
  reg[3:0] in0, in1, in2, in3, in4, in5;
  reg[2:0] opt;
  reg equ;
  wire[3:0] final_out;

  
  CC c1(
    .in_n0(in0), 
    .in_n1(in1), 
    .in_n2(in2), 
    .in_n3(in3), 
    .in_n4(in4), 
    .in_n5(in5), 
    .opt(opt), 
    .equ(equ), 
    .out_n(final_out));
  
  initial begin
    //$dumpfile("dump.vcd");
    $dumpvars(0, test); // 有這個才會有報告出來
    
    #20;                // 應該是設定時間標籤的樣子
    in0 = 4'b1000;
    in1 = 4'b1000;
    in2 = 4'b1000;
    in3 = 4'b1000;
    in4 = 4'b1000;
    in5 = 4'b1000;    
    
    opt = 3'b000;
    equ = 1'b0;
    
    #20;
    in0 = 4'b0100;
    
    #20 $finish;
    
  end
endmodule

## 小筆記

一個 always block 最好只設定一個 register

## 疑問

Q: 一個 module 的輸出，可以是 wire 或是 register 嗎？
A: 看 Practice 給的範例，應該是這樣沒錯

Q: signed wire 把值給 wire 好像會打X，怎麼解決？？？
A: 後來又不打叉了....Oh WOW

Q: 規格書上寫最後的輸出是有號數，但是我把數字填滿後，

-------------------------------------------------------------------
*                            PATTERN NO.   0 	                
             answer should be :   48 , your answer is : 1023           
-------------------------------------------------------------------

跑出的是無號數？？？
*-> 就算是 signed 的 wire ， 在賦值的時候也是不會幫你 signed extension 的

## 要做的事

opt - unsigned/signed
opt - sort
opt - normalize

equ - equ0
equ - equ1

## 資源

[1][Wikipedia: Adder–subtractor](https://en.wikipedia.org/wiki/Adder%E2%80%93subtractor)
[2][線上撰寫verilog，並查看波形](https://www.edaplayground.com/)
[3][線上課程：verilog](https://www.youtube.com/watch?v=bL3ihMA8_Gs&hd=1)
[4][verilog:slideshare](https://www.slideshare.net/itembedded/verilog-14596615)
[5][Wikipedia: Subtractor](https://en.wikipedia.org/wiki/Subtractor)

###### tags: `ic lab`